Semiconductor package having a solder-on-pad structure
View Patent ↗A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.
1. A semiconductor package, comprising:
a substrate comprising a first face and an opposing second face;
at least one pad provided on the first face of the substrate, the at least one pad comprising an outward facing surface that is substantially parallel and non-overlapping with the first face of the substrate and one or more side edges that separate the outward facing surface from the first face of the substrate, and wherein the at least one pad provides electrical connectivity to other electrical components mounted to the substrate; and
at least one solder-on-pad structure formed on the outward facing surface of the at least one pad, wherein the at least one solder-on-pad structure covers and overlaps a first portion of the outward facing surface, and wherein a second portion of the outward facing surface is not overlapped by the at least one solder-on-pad structure and is exposed prior to the at least one solder-on-pad structure being connected to a Printed Circuit Board (PCB).
2. The semiconductor package of claim 1 , wherein the second portion of the outward facing surface is adjacent to the first portion of the outward facing surface and is exposed to environmental conditions.
3. The semiconductor package of claim 1 , further comprising a first circuit element mounted on the at least one pad via the at least one solder-on-pad structure.
4. The semiconductor package of claim 3 , wherein the first circuit element comprises a passive circuit element.
5. The semiconductor package of claim 3 , wherein a side edge of the first circuit element is substantially aligned with a side edge of the at least one pad.
6. The semiconductor package of claim 1 , wherein the at least one pad comprises a plurality of pads formed in an array.
7. The semiconductor package of claim 1 , wherein the at least one pad comprises a first solder-on-pad structure and a second solder-on-pad structure deposited on the outward facing surface.
8. The semiconductor package of claim 1 , wherein the at least one solder-on-pad structure is formed directly on the outward facing surface of the at least one pad by printing material of the at least one solder-on-pad structure onto the outward facing surface of the at least one pad.
9. The semiconductor package of claim 1 , wherein a flux material is used to help adhesion of the at least one solder-on-pad structure to the outward facing surface of the at least one pad.
10. The semiconductor package of claim 1 , wherein the solder-on-pad structure is coined.
11. The semiconductor package of claim 3 , wherein the first circuit element comprises a first side edge and a second side edge, wherein the at least one pad comprises a first pad and a second pad, and wherein the first circuit element is connected between the first pad and the second pad.
12. The semiconductor package of claim 11 , wherein the first circuit element comprises a passive circuit element having only two electrical terminals for external electrical connections.
13. The semiconductor package of claim 12 , wherein a first side edge of the first circuit element is substantially aligned with a first side edge of the first pad and wherein a second side edge of the first circuit element is substantially aligned with a first side edge of the second pad.
14. The semiconductor package of claim 13 , wherein the first side edge of the first circuit element and the second side edge of the first circuit element are substantially perpendicular with respect to the first face of the substrate.
15. The semiconductor package of claim 13 , further comprising a second circuit element, wherein a spacing between the first circuit element and the second circuit element is substantially equal to a spacing between the first pad and the second pad.
16. The semiconductor package of claim 11 , wherein the first pad and the second pad are surrounded by a dielectric material that is substantially devoid of a solder resist material.
17. The semiconductor package of claim 1 , wherein the substrate comprises a residue of a sacrifice material adjacent to the at least one pad.
18. The semiconductor package of claim 1 , wherein the at least one solder-on-pad structure is formed directly on the outward facing surface of the at least one pad prior to having a circuit element connected thereto.
19. The semiconductor package of claim 1 , wherein the one or more side edges of the at least one pad are substantially flat.
20. The semiconductor package of claim 1 , wherein the one or more side edges of the at least one pad are substantially curved.