Lateral power MOSFET with non-horizontal RESURF structure
In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.
1. A lateral insulated gate transistor formed in a semiconductor substrate comprising:
a first region of a first conductivity type;
a second region of the first conductivity type;
a body region of a second conductivity type;
a lateral gate insulated from and overlying at least a portion of the body region, wherein the portion of the body region forms a channel, the lateral gate being separated from the channel by a first gate dielectric thickness;
a third region of the first conductivity type under the lateral gate and abutting the body region, the third region having a dopant concentration less than a dopant concentration of the first region, the third region having a depth that is less than a lateral dimension of the third region extending from the body region and under the lateral gate toward the second region;
a Reduced Surface Field (RESURF) structure comprising alternating layers of a first material of the first conductivity type and a second material of the second conductivity type, the alternating layers of the first material and the second material overlying each other, the alternating layers in a first portion of the RESURF structure running parallel to a top surface of the semiconductor substrate toward the second region, and the alternating layers in a second portion of the RESURF structure inclining upward toward the lateral gate such that ends of the alternating layers in the second portion of the RESURF structure face the lateral gate,
wherein the ends of the alternating layers of the first material of the first conductivity type in the second portion of the RESURF structure terminate at a bottom of the third region, wherein the bottom of the third region is above a bottom of the body region,
wherein the lateral gate overlies the third region from between the body region to where the alternating layers of the first material and the second material terminate in the third region, and wherein the lateral gate is separated from the third region, from between the body region to where the alternating layers of the first material and the second material terminate in the third region, by the first gate dielectric thickness;
wherein the lateral insulated gate transistor is configured such that, upon a threshold voltage being applied to the lateral gate, a conductive channel is formed in the body region by inversion of the body region under the lateral gate, such that a current flows between the first region and the second region through the third region and RESURF structure,
wherein the third region is configured such that, when the conduction channel is formed, current flows laterally through the third region, then through the RESURF structure.
2. The lateral insulated gate transistor of claim 1 wherein the doping concentration of the third region, abutting the body region, is selected to at least partially offset a charge imbalance caused by the body region and to be depleted when the lateral insulated gate transistor is in its off state.
3. The lateral insulated gate transistor of claim 1 wherein the alternating layers of the first material and the second material terminate in the third region of the first conductivity type under the lateral gate, and also terminate in a fourth region of the second conductivity under the lateral gate.
4. The lateral insulated gate transistor of claim 1 wherein the first conductivity type is an N-type, the second conductivity type is a P-type, the first region is a source, and the second region is a drain.
5. The lateral insulated gate transistor of claim 1 wherein there are at least nine alternating layers of the first material and the second material.
6. The lateral insulated gate transistor of claim 1 further comprising a buffer region of the first conductivity type adjacent to the second region, wherein the alternating layers of the first material and the second material terminate at the buffer region.
7. The lateral insulated gate transistor of claim 1 wherein the lateral insulated gate transistor is configured such that, upon the threshold voltage being applied to the lateral gate, the conductive channel is formed in the body region by inversion of the body region under the lateral gate, and one or more of the alternating layers are inverted under the lateral gate, such that the current flows between the first region and the second region through the RESURF structure.
8. The lateral insulated gate transistor of claim 1 wherein the lateral insulated gate transistor comprises a plurality of identical cells electrically connected in parallel, wherein each cell has an identical RESURF structure.
9. The lateral insulated gate transistor of claim 1 further comprising a bottom metal layer electrically coupled to the first region.
10. The lateral insulated gate transistor of claim 9 wherein the semiconductor substrate is a P-type, and the second conductivity type is a P-type, the lateral insulated gate transistor further comprising a P+ type layer forming at least a portion of a bottom semiconductor surface of the lateral insulated gate transistor on which the bottom metal layer is formed for creating a vertical clamp diode anode.
11. The lateral insulated gate transistor of claim 9 wherein the semiconductor substrate is an N-type, and the second conductivity type is a P-type, the lateral insulated gate transistor further comprising an N+ type layer forming at least a portion of a bottom semiconductor surface of the lateral insulated gate transistor on which the bottom metal layer is formed for creating a vertical clamp diode cathode.
12. The lateral insulated gate transistor of claim 1 wherein the lateral insulated gate transistor is a lateral MOSFET.
13. The lateral insulated gate transistor of claim 1 wherein the lateral insulated gate transistor is an Insulated Gate Bipolar Transistor (IGBT), the IGBT further comprising:
a fourth region of the second conductivity type adjacent to the second region, wherein the fourth region is a collector of the IGBT; and
a fifth region formed in the body region being an emitter of the IGBT,
wherein, when the threshold voltage is applied to the lateral gate to create the conductive channel, the current flowing between the first region and the fourth region turns on a lateral bipolar transistor comprising the fourth region, the body region, and the fifth region.
14. The lateral insulated gate transistor of claim 13 further comprising:
a bottom metal layer electrically coupled to the fifth region; and
a sixth region formed in a bottom surface of the semiconductor substrate and contacted by the bottom metal layer for forming a diode.
15. The lateral insulated gate transistor of claim 14 wherein the semiconductor substrate is the second conductivity type, and the sixth region is of the second conductivity type for forming a clamp diode.
16. The lateral insulated gate transistor of claim 14 wherein the semiconductor substrate is the first conductivity type, and the sixth region is of the first conductivity type for forming the diode for conducting a reverse current through the IGBT when forward biased.
17. The lateral insulated gate transistor of claim 1 wherein the RESURF structure forms concentric rings of the alternating layers.
18. The lateral insulated gate transistor of claim 1 wherein the alternating layers of the first material and the second material also incline upward toward a top surface of the lateral insulated gate transistor proximate to the second region.
19. A lateral insulated gate transistor formed in a semiconductor substrate comprising:
a first region of a first conductivity type;
a second region of the first conductivity type;
a body region of a second conductivity type;
a gate insulated from the body region;
a plurality of trenches formed between the gate and the second region, the plurality of trenches running alongside each other and running perpendicular with respect to a direction of current flow between the first region and the second region, each trench in the plurality of trenches having a first sidewall and a second sidewall, the plurality of trenches not containing the gate, the plurality of trenches including a first trench proximate to the first region and a last trench further from the first region and proximate to the second region; and
a Reduced Surface Field (RESURF) structure comprising repeating alternating layers of a first material of the first conductivity type and a second material of the second conductivity type,
the repeating alternating layers running perpendicular to the first sidewall of each trench in the plurality of trenches and the second sidewall of each trench in the plurality of trenches, the repeating alternating layers being a drift region between the first region and the second region in the lateral insulated gate transistor, wherein the first sidewalls face in a direction of the first region, and the second sidewalls face in a direction of the second region, wherein each of the repeating alternating layers is continuous from the first trench to the last trench,
wherein the lateral insulated gate transistor is configured such that, upon a threshold voltage being applied to the gate, a conductive channel is formed in the body region by inversion of the body region proximate to the gate such that a current flows between the first region and the second region through the RESURF structure.
20. The lateral insulated gate transistor of claim 19 wherein the lateral insulated gate transistor is a MOSFET.