Semiconductor component and method of manufacture

1. A semiconductor component, comprising:

a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead;

a first semiconductor chip having a first surface and a second surface, wherein a first gate bond pad extends from a first portion of the first surface, a source bond pad extends from a second portion of the first surface, and a drain bond pad extends from a third portion of the first surface, the second surface of the first semiconductor chip bonded to the first device receiving structure, the first semiconductor chip configured from a silicon semiconductor material;

a second semiconductor chip having a first surface and a second surface, a gate bond pad of the second semiconductor chip extends from a first portion of the first surface of the second semiconductor chip, a source bond pad of the second semiconductor chip extends from a second portion of the first surface of the second semiconductor chip, and a drain bond pad extends from a third portion of the first surface of the second semiconductor chip, the second semiconductor chip configured from a III-nitride semiconductor material, the source bond pad of the second semiconductor chip electrically coupled to the drain bond pad of the first semiconductor chip, the gate bond pad of the second semiconductor chip electrically coupled to the source bond pad of the first semiconductor chip, and the drain bond pad of the second semiconductor chip electrically coupled to the second device receiving structure;

a first electrical interconnect coupled between the gate bond pad of the first semiconductor device and the first lead; and

a second electrical interconnect coupled between the source bond pad of the first semiconductor chip and the third lead.

2. The semiconductor component of claim 1 , further including a third electrical interconnect coupled between the second lead and the source bond pad of the first semiconductor chip.

3. The semiconductor component of claim 2 , wherein the first electrical interconnect is a bond wire, the third electrical interconnect is a bond wire, and the second electrical interconnect is a first clip.

4. The semiconductor component of claim 2 , wherein the first electrical interconnect is a bond wire, the third electrical interconnect is a first portion of a clip, and the second electrical interconnect is a second portion of a clip.

5. The semiconductor component of claim 1 , wherein the second device receiving structure includes a pedestal.

6. The semiconductor component of claim 1 , further including a third electrical interconnect coupled between the second surface of the second semiconductor chip and the drain bond pad of the first semiconductor chip.

7. The semiconductor component of claim 1 , wherein the second semiconductor chip is coupled to the first semiconductor chip in a flip-chip configuration.

8. The semiconductor component of claim 1 , wherein the second device receiving structure comprises a first electrically conductive structure, a second electrically conductive structure, and a third electrically conductive structure.

9. The semiconductor component of claim 8 , wherein the second surface of the first semiconductor chip is coupled to a first portion of a mold compound and second device receiving structure comprises a first electrically conductive structure and a second electrically conductive structure, a second portion of the mold compound between the first electrically conductive structure and the second electrically conductive structure.

10. The semiconductor component of claim 9 , wherein the source bond pad of the second semiconductor chip is electrically coupled to the first electrically conductive material of the first device receiving structure and the drain bond pad of the second semiconductor chip is electrically coupled to a first portion of the second device receiving structure and the gate bond pad of the second semiconductor chip is electrically coupled to a second portion of the second device receiving structure.

11. The semiconductor component of claim 10 , wherein the drain bond pad of the first semiconductor chip is electrically coupled to the first electrically conductive structure of the second device receiving structure.

12. The semiconductor component of claim 11 , wherein the drain bond pad of the first semiconductor chip is electrically coupled to the first electrically conductive structure of the second device receiving structure by a first clip.

13. The semiconductor component of claim 12 , further including a first bond wire coupled between the source bond pad of the first semiconductor chip and the third electrically conductive structure of the second device receiving structure.

14. The semiconductor component of claim 12 , further including a second clip coupled between the first clip and the second surface of the second semiconductor chip.

15. A semiconductor component, comprising:

a support comprising an electrically conductive substrate having a first surface and a second surface, the support further including a first lead, a second lead, and a third lead;

a first dielectric material coupled to a first portion of the first surface of the support;

a first semiconductor chip having a first surface and a second surface, wherein a first gate bond pad extends from a first portion of the first surface of the first semiconductor chip, a source bond pad extends from a second portion of the first surface of the first semiconductor chip, and a drain bond pad extends from a third portion of the first surface of the first semiconductor chip, the second surface of the first semiconductor chip bonded to the first dielectric material, the first semiconductor chip configured from a silicon semiconductor material;

a second semiconductor chip having a first surface and a second surface, a gate bond pad of the second semiconductor chip extends from a first portion of the first surface of the second semiconductor chip a source bond pad of the second semiconductor chip extends from a second portion of the first surface of the second semiconductor chip, and a drain bond pad extends from a third portion of the first surface of the second semiconductor chip, the second semiconductor chip configured from a III-nitride semiconductor material, the source bond pad of the second semiconductor chip electrically coupled to the drain bond pad of the first semiconductor chip, the gate bond pad of the second semiconductor chip electrically coupled to the source bond pad of the first semiconductor chip, and the drain bond pad of the second semiconductor chip electrically coupled to the support;

a first electrical interconnect coupled between the gate bond pad of the first semiconductor chip and the first lead; and

a second electrical interconnect coupled between the source bond pad of the first semiconductor chip and the second lead.

16. The semiconductor component of claim 15 , wherein the second semiconductor chip is electrically coupled to the first semiconductor chip in a flip chip configuration.

17. The semiconductor component of claim 15 , wherein the first lead, the second lead, and the third lead are electrically isolated from the electrically conductive substrate.

18. A method for manufacturing a semiconductor component, comprising:

providing a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead;

coupling a first semiconductor chip to the first device receiving area, the first semiconductor chip having a first surface and a second surface, wherein a first gate bond pad extends from a first portion of the first surface, a source bond pad extends from a second portion of the first surface, and a drain bond pad extends from a third portion of the first surface, the second surface of the first semiconductor chip bonded to the first device receiving structure, the first semiconductor chip configured from a silicon semiconductor material;

coupling a second semiconductor chip to the second device receiving area, the second semiconductor chip having a first surface and a second surface, a gate bond pad of the second semiconductor chip extends from a first portion of the first surface of the second semiconductor chip, a source bond pad of the second semiconductor chip extends from a second portion of the first surface of the second semiconductor chip, and a drain bond pad extends from a third portion of the first surface of the second semiconductor chip, the second semiconductor chip configured from a gallium nitride semiconductor material, the source bond pad of the second semiconductor chip electrically coupled to the drain bond pad of the first semiconductor chip, the gate bond pad of the second semiconductor chip electrically coupled to the source bond pad of the first semiconductor chip, and the drain bond pad of the second semiconductor chip electrically coupled to the second device receiving structure;

electrically coupling the gate bond pad of the first semiconductor device to the first lead; and

electrically coupling the source bond pad of the first semiconductor chip to the second lead.

19. The method of claim 18 , wherein coupling the second semiconductor chip to the second device receiving area includes flip chip bonding the second semiconductor chip to the second device receiving area.

20. The method of claim 19 , wherein coupling the second semiconductor chip to the second device receiving area includes coupling a first portion of the second semiconductor chip to the first semiconductor chip and coupling a second portion of the second semiconductor chip to the second device receiving area.