Semiconductor memory device capable of reducing peak current with respect to external power in multi-memory die structures

1. A semiconductor memory device comprising:

a plurality of memory dies including a first memory die and additional memory dies;

a plurality of charge pump circuits installed on the plurality of memory dies, wherein the plurality of charge pump circuits includes a first charge pump circuit installed on the first memory die; and

a first pump managing circuit which is installed on the first memory die, the first pump managing circuit configured to control the first charge pump circuit and receive operation state information with respect to the additional memory dies to generate one or more control signals for controlling the first charge pump circuit,

wherein the one or more control signals comprise a signal that changes an oscillating clock period of an oscillating clock applied to the first charge pump circuit based on the operation state information of the additional memory dies.

2. The semiconductor memory device of claim 1 , wherein the operation state information includes a power-up state with respect to additional memory dies.

3. The semiconductor memory device of claim 1 , wherein the one or more control signals are further based on a current operation mode with respect to the first memory die.

4. The semiconductor memory device of claim 1 , wherein the one or more control signals are further based on a voltage level detection information with respect to the first memory die.

5. The semiconductor memory device of claim 1 , wherein the one or more control signals comprise a signal for turning on or off the first charge pump circuit.

6. The semiconductor memory device of claim 1 , wherein the one or more control signals comprise a signal for involving pumping drive devices in the first charge pump circuit in a charge pumping operation.

7. The semiconductor memory device of claim 1 , wherein the first memory die is configured so that the additional memory dies of the plurality of memory dies whose operation state information will be used to control the first charge pump circuit is set in advance.

8. The semiconductor memory device of claim 1 , wherein each memory die includes a plurality of charge pump circuits, and the one or more control signals control the plurality of charge pump circuits of the first memory die.

9. The semiconductor memory device of claim 1 , wherein the first pump managing circuit receives the operation state information with respect to the additional memory dies from the additional memory dies.

10. The semiconductor memory device of claim 1 , wherein the first pump managing circuit is configured to generate the one or more controls signals for controlling the first charge pump circuit based on the operation state information of the additional memory dies.

11. A semiconductor memory device comprising:

a plurality of memory dies;

a plurality of voltage generators, wherein one voltage generator of the plurality of voltage generators is installed on one memory die of the plurality of memory dies and other voltage generators of the plurality of voltage generators are installed on other memory dies of the plurality of memory dies; and

power managing circuits, wherein one power managing circuit of the power managing circuits is installed on the one voltage generator of the plurality of voltage generators to manage the whole power of a package by controlling the one voltage generator and receiving operation state information with respect to the other memory dies to generate control signals for controlling the one voltage generator installed on the one memory die,

wherein the control signals comprise a signal that changes an oscillating clock period of an oscillating clock applied to the one voltage generator based on the operation state information of the other memory dies.

12. The semiconductor memory device of claim 11 , wherein the memory dies are vertically stacked on a substrate.

13. The semiconductor memory device of claim 11 , wherein each of the memory dies receives an address, a command, or data through a through substrate via.

14. The semiconductor memory device of claim 11 , wherein the memory dies are horizontally disposed with respect to each other and are connected in common to one memory controller.

15. A semiconductor memory device comprising:

a plurality of memory dies;

a plurality of charge pump circuits, wherein one charge pump circuit of the plurality of charge pump circuits is installed on one memory die of the plurality of memory dies and other charge pump circuits of the plurality of charge pump circuits are installed on other memory dies of the plurality of memory dies; and

a plurality of pump managing circuits, wherein one pump managing circuit of the plurality of pump managing circuits is installed on one of the memory dies to control the one charge pump circuit and receive operation state information with respect to the other memory dies to generate control signals for controlling the one charge pump circuit installed on the one memory die,

wherein the control signals comprise a signal that changes an oscillating clock period of an oscillating clock applied to the one charge pump circuit based on the operation state information of the other memory dies.

16. The semiconductor memory device of claim 15 , wherein the control signals are based on a current operation mode with respect to the one memory die.

17. The semiconductor memory device of claim 15 , wherein the control signals are based on voltage level detection information with respect to the one memory die.

18. The semiconductor memory device of claim 15 , wherein the control signals comprise a signal for turning on or off additional charge pump circuits installed on the one memory die.