Termination for a stacked-gate super-junction MOSFET
View Patent ↗At least some illustrative device embodiments include a highly-doped n-type semiconductor substrate having a first epitaxial layer of a lightly-doped n-type semiconductor; and a second epitaxial layer of a lightly-doped p-type semiconductor to form a vertical diode with the first epitaxial layer. A termination structure near the outer edges of the device includes a termination well in the second epitaxial layer, the termination well being a moderately-doped n-type semiconductor so as to form a horizontal diode with the second epitaxial layer. The structure further includes an electric field barrier. The electric field barrier includes at least one vertical trench extending through the termination well into the first epitaxial layer and exposing a sidewall region. The sidewall region is doped via the sidewalls to be a moderately-doped p-type semiconductor. Also provided are sidewall layers of a moderately-doped n-type semiconductor, the sidewalls electrically coupling the termination well to the substrate.
1. A semiconductor device that comprises:
a substrate, the substrate being a highly-doped semiconductor of a first type;
a first epitaxial layer on the substrate, the first epitaxial layer being a lightly-doped semiconductor of the first type;
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a lightly-doped semiconductor of a second type to form a vertical diode with the first epitaxial layer;
an edge termination structure comprising:
a termination well in the second epitaxial layer, the termination well being a moderately-doped semiconductor of the first type to form a horizontal diode with the second epitaxial layer; and
an electric field barrier including:
at least one vertical trench extending through the termination well into the first epitaxial layer and exposing a sidewall region, the sidewall region being doped via trench sidewalls to be a moderately-doped semiconductor of the second type; and
sidewall layers in the at least one vertical trench, the sidewall layers comprising a moderately-doped semiconductor of the first type that electrically couples the termination well to the substrate.
2. The semiconductor device of claim 1 , wherein the electric field barrier further comprises a conductive trench fill material.
3. The semiconductor device of claim 2 , further comprising:
an interlayer dielectric over the second epitaxial layer; and
a drain seal ring over the interlayer dielectric above the electric field barrier, wherein the drain seal ring connects to the conductive trench fill material.
4. The semiconductor device of claim 1 , wherein the electric field barrier further comprises an insulating trench fill material.
5. The semiconductor device of claim 4 , further comprising:
a gate recessed into the insulating trench fill material;
an interlayer dielectric over the second epitaxial layer; and
a drain seal ring over the interlayer dielectric above the electric field barrier, wherein the drain seal ring connects to the gate.
6. The semiconductor device of claim 1 , wherein the edge termination structure further comprises a physical barrier around the electric field barrier, the physical barrier including:
a second vertical trench extending through the termination well into the first epitaxial layer and exposing a sidewall region, the sidewall region being doped via trench sidewalls to be a moderately-doped semiconductor of the second type;
sidewall layers in the second vertical trench, the sidewall layers comprising a moderately-doped semiconductor of the first type that electrically couples the termination well to the substrate; and
a trench fill layer between the sidewall layers.
7. The semiconductor device of claim 6 , wherein the trench fill layer comprises silicon dioxide.
8. The semiconductor device of claim 6 , wherein the edge termination structure further comprises a current barrier enclosed by the electric field barrier, the current barrier including:
a third vertical trench extending from a surface of the second epitaxial layer down into the first epitaxial layer and exposing a sidewall region, the sidewall region being doped via trench sidewalls to be a moderately-doped semiconductor of the second type;
sidewall layers in the third vertical trench, the sidewall layers comprising a moderately-doped semiconductor of the first type and that electrically couple to the substrate; and
an insulating trench fill layer between the sidewall layers.
9. The semiconductor device of claim 8 , wherein said first type is n-type and said second type is p-type.
10. The semiconductor device of claim 8 , wherein said first type is p-type and said second type is n-type.