SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE
A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
1 . A power electronic substrate, comprising:
a dielectric layer comprising a first surface and a second surface opposing the first surface;
a ceramic layer having a bonding pattern on a second surface of the ceramic layer, the second surface of the ceramic layer laminated with the first surface of the dielectric layer, the first surface of the dielectric layer configured to receive the bonding pattern of the second surface of the ceramic layer; and
a plurality of copper traces, each copper trace coupled to the dielectric layer at the second surface of the dielectric layer and at a first surface of the copper trace.
2 . The power electronic substrate of claim 1 , wherein the dielectric layer comprises an epoxy.
3 . The power electronic substrate of claim 1 , wherein a first surface of the ceramic layer comprises a bonding pattern, the first surface of the ceramic layer laminated with a second surface of a second dielectric layer, the second surface of the second dielectric layer configured to receive the bonding pattern of the first surface of the ceramic layer, the power electronic substrate further comprising a metallic baseplate having a first surface and a second surface, the second surface of the metallic baseplate opposite the first surface of the metallic baseplate, the second surface of the metallic baseplate coupled to a first surface of the second dielectric layer opposing the second surface of the second dielectric layer.
4 . The power electronic substrate of claim 1 , wherein the bonding pattern of the second surface of the ceramic layer comprises bonding ridges.
5 . The power electronic substrate of claim 1 , wherein the bonding pattern of the second surface of the ceramic layer comprises one of conical projections and pyramidal projections.
6 . The power electronic substrate of claim 1 , wherein the plurality of copper traces comprise at least two trace thicknesses of different magnitudes measured along a direction substantially perpendicular to the second surface of the metallic baseplate.