Power management in multi-die assemblies
An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.
1. An apparatus comprising:
a plurality of integrated circuit semiconductor dies in a common package;
power management circuitry on one of the plurality of dies to receive an input voltage for the common package, the power management circuitry including
a first inductive element;
a second inductive element magnetically coupled to the first inductive element; and
switching circuitry to control a current through the first inductive element to produce a first voltage different from the input voltage to power one of the plurality of integrated circuit semiconductor dies, and to induce a current through the second inductive element to produce a second voltage different from the first voltage to power another of the plurality of integrated circuit semiconductor dies.
2. The apparatus of claim 1 , wherein the plurality of integrated circuit semiconductor dies comprises a vertical stack of dies.
3. The apparatus of claim 2 , wherein the power management circuitry is to deliver the first and second voltages via one or more through-silicon vias (TSVs).
4. The apparatus of claim 1 , wherein the plurality of integrated circuit semiconductor dies comprises semiconductor dies of different semiconductor technologies.
5. The apparatus of claim 1 , wherein the plurality of integrated circuit semiconductor dies comprises multiple memory device dies.
6. The apparatus of claim 1 , wherein the plurality of integrated circuit semiconductor dies comprises a base die and one or more memory device dies.
7. The apparatus of claim 1 , wherein the plurality of integrated circuit semiconductor dies comprises one or more memory device dies and one or more non-memory device dies.
8. The apparatus of claim 1 , wherein the power management circuitry comprises a voltage regulator with the inductive elements.
9. The apparatus of claim 7 , wherein the first and second voltages comprise a first voltage different than the input voltage to power the memory device dies and a second voltage different from the first voltage to power the non-memory device dies.
10. The apparatus of claim 1 , wherein the power management circuitry comprises a third inductive element magnetically coupled to the first inductive element to produce a third voltage different from the first and second voltages to power a different one of the plurality of integrated circuit semiconductor dies.
11. A multi-die package comprising:
a logic die to receive an input voltage for the multi-die package;
a vertical stack of a plurality of semiconductor dies on the logic die; and
power management circuitry on the logic die to generate at least one voltage different from the input voltage of the plurality of semiconductor dies, the power management circuitry including
a first inductive element;
a second inductive element magnetically coupled to the first inductive element; and
switching circuitry to control a current through the first inductive element to produce a first voltage different from the input voltage to power one of the plurality of semiconductor dies, and to induce a current through the second inductive element to produce a second voltage different from the first voltage to power another of the semiconductor dies.
12. The package of claim 11 , wherein the power management circuitry is to deliver the first and second voltages via one or more through-silicon vias (TSVs).
13. The package of claim 11 , wherein the plurality of semiconductor dies comprises multiple memory chips.
14. The package of claim 13 , wherein the multiple memory chips comprises at least one non-volatile memory chip.
15. The package of claim 13 , wherein the multiple memory chips comprises at least one volatile memory chip.
16. The package of claim 11 , wherein the plurality of semiconductor dies comprises one or more memory device dies and one or more non-memory device dies.
17. The package of claim 11 , wherein the power management circuitry comprises a voltage regulator with the inductive elements.
18. The package of claim 16 , wherein the first and second voltages comprise a first voltage different than the input voltage to power the memory device dies and a second voltage different from the first voltage to power the non-memory device dies.
19. The package of claim 11 , wherein the power management circuitry comprises a third inductive element magnetically coupled to the first inductive element to produce a third voltage different from the first and second voltages to power a different one of the plurality of semiconductor dies.