Multi terminal capacitor within input output path of semiconductor package interconnect
A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
1. A semiconductor device fabrication method comprising:
forming a solder mask upon a lower surface of a semiconductor chip carrier;
forming a first opening and a neighboring second opening in the solder mask to expose a first input output (IO) contact and a neighboring second IO contact of the semiconductor chip carrier;
attaching a multi terminal capacitor to the semiconductor chip carrier such that a first terminal contacts the first IO contact and a second terminal contacts the second IO contact; and
interconnecting the semiconductor chip carrier with a carrier interposer with solder interconnects such that a first solder interconnect directly contacts the first terminal and the first IO contact and a second solder interconnect directly contacts the second terminal and the second IO contact.
2. The semiconductor device fabrication method of claim 1 , wherein there is no inductance between the first solder interconnect and the first terminal and between the first solder interconnect and the first IO contact.
3. The semiconductor device fabrication method of claim 1 , further comprising:
placing the first solder interconnect within the first opening and upon the first IO contact; and
placing the second solder interconnect within the second opening and upon the second IO contact.
4. The semiconductor device fabrication method of claim 1 , further comprising:
reflowing the solder interconnects.
5. The semiconductor device fabrication method of claim 1 , wherein the solder interconnects is a micro ball grid array.
6. The semiconductor device fabrication method of claim 1 , further comprising:
forming a capacitor trench within the solder mask between the first opening and the second opening.
7. The semiconductor device fabrication method of claim 6 , wherein attaching a multi terminal capacitor to the semiconductor chip carrier comprises:
attaching the multi terminal capacitor to the solder mask within the capacitor trench.
8. The semiconductor device fabrication method of claim 1 , wherein the first opening comprises a first capacitor tab and the second opening comprises a second capacitor tab.
9. The semiconductor device fabrication method of claim 8 , wherein the first terminal contacts the first IO contact within the first capacitor tab and a second terminal contacts the second IO contact within the second capacitor tab.
10. The semiconductor device fabrication method of claim 8 , wherein the first opening further comprises a first signal tab and the second opening comprises a second signal tab.
11. A semiconductor device fabrication method comprising:
forming a solder mask upon an upper surface of a carrier interposer;
forming a first opening and a neighboring second opening in the solder mask to expose a first input output (IO) contact and a neighboring second IO contact of the carrier interposer;
attaching a multi terminal capacitor to the carrier interposer such that a first terminal contacts the first IO contact and a second terminal contacts the second IO contact; and
interconnecting the carrier interposer with a semiconductor chip carrier with solder interconnects such that a first solder interconnect directly contacts the first terminal and the first IO contact and a second solder interconnect directly contacts the second terminal and the second IO contact.
12. The semiconductor device fabrication method of claim 11 , wherein there is no inductance between the first solder interconnect and the first terminal and between the first solder interconnect and the first IO contact.
13. The semiconductor device fabrication method of claim 11 , further comprising:
placing the first solder interconnect within the first opening and upon the first IO contact; and
placing the second solder interconnect within the second opening and upon the second IO contact.
14. The semiconductor device fabrication method of claim 11 , further comprising:
reflowing the solder interconnects.
15. The semiconductor device fabrication method of claim 11 , wherein the solder interconnects are a micro ball grid array.
16. The semiconductor device fabrication method of claim 11 , further comprising:
forming a capacitor trench within the solder mask between the first opening and the second opening.
17. The semiconductor device fabrication method of claim 16 , wherein attaching a multi terminal capacitor to the semiconductor chip carrier comprises:
attaching the multi terminal capacitor to the solder mask within the capacitor trench.
18. The semiconductor device fabrication method of claim 11 , wherein the first opening comprises a first capacitor tab and the second opening comprises a second capacitor tab.
19. The semiconductor device fabrication method of claim 18 , wherein the first terminal contacts the first IO contact within the first capacitor tab and a second terminal contacts the second IO contact within the second capacitor tab.