High thermal budget compatible punch through stop integration using doped glass
A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
1. A semiconductor device comprising:
a fin structure including an active portion and an isolating portion, the active portion comprising a channel region and source and drain regions on opposing sides of the channel region, wherein the isolating portion of the fin structure includes a doped punch through stop region that is present underlying the channel region and the source and drain regions of the active portion;
a spacer of doped glass present on the isolation portion of the fin structure, wherein the spacer of doped glass is not present on the active portion;
a vertically orientated hardmask dielectric spacer present on the spacer of the doped glass, wherein the vertically orientated hardmask dielectric spacer does not include a horizontally orientated portion over a substrate that the fin structure is present on; and
a gate structure present on the channel region of the active portion of the fin structure.
2. The semiconductor device of claim 1 , wherein said source and drain regions are doped to a first conductivity type and the punch through stop region is doped to a second conductivity type, said second conductivity type being opposite the first conductivity type.
3. The semiconductor device of claim 1 , wherein a charge carrier type dopant in said source and drain region is present in a concentration ranging from 1×10 20 atoms/cm 3 to 2×10 20 atoms/cm 3 .
4. The semiconductor device of claim 1 , wherein punch through dopant in said doped punch through stop region in said isolating portion of said fin structure is present in a concentration ranging from 4×10 18 atoms/cm 3 to 3×10 19 atoms/cm 3 .
5. The semiconductor device of claim 1 , wherein a tail of said punch through dopant is present in the active portion extending away from the isolation portion of said fin structure in reducing concentration.
6. The semiconductor device of claim 1 , wherein concentration of said punch through dopant in said tail ranges from 1×10 17 atoms/cm 3 to 1×10 18 atoms/cm 3 .
7. A semiconductor device comprising:
a fin structure including an active portion and an isolating portion, the active portion comprising a channel region and source and drain regions on opposing sides of the channel region, wherein the isolating portion of the fin structure includes a doped punch through stop region that is present underlying the channel region and the source and drain regions of the active portion;
a spacer of doped glass present on the isolation portion of the fin structure, wherein the spacer of doped glass is not present on the active portion; and
a vertically orientated hardmask dielectric spacer present on the spacer of the doped glass, wherein the vertically orientated hardmask dielectric spacer does not include a horizontally orientated portion over a substrate that the fin structure is present on.
8. The semiconductor device of claim 7 , wherein said source and drain regions are doped to a first conductivity type and the punch through stop region is doped to a second conductivity type, said second conductivity type being opposite the first conductivity type.
9. The semiconductor device of claim 7 , wherein a charge carrier type dopant in said source and drain region is present in a concentration ranging from 1×10 20 atoms/cm 3 to 2×10 20 atoms/cm 3 .
10. The semiconductor device of claim 7 , wherein punch through dopant in said doped punch through stop region in said isolating portion of said fin structure is present in a concentration ranging from 4×10 18 atoms/cm 3 to 3×10 19 atoms/cm 3 .
11. The semiconductor device of claim 7 , wherein a tail of said punch through dopant is present in the active portion extending away from the isolation portion of said fin structure in reducing concentration.
12. The semiconductor device of claim 7 , wherein concentration of said punch through dopant in said tail ranges from 1×10 17 atoms/cm 3 to 1×10 18 atoms/cm 3 .
13. The semiconductor device of claim 7 , wherein the doped glass of the spacer is selected from the group consisting of borosilicateglass (BSG) (p-type silicate glass), phosphosilicate glass (PSG)(n-type silicate glass), arsenosilicate glass (ASG)(n-type silicate glass) and combinations thereof.