Semiconductor device and manufacturing method thereof
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
1. A method of manufacturing a semiconductor device, comprising:
forming a first and a second stacked structure of a non-volatile memory over a substrate;
forming a conductive material layer over the first and second stacked structures;
forming a planarization layer over the conductive material layer;
forming a mask pattern over the planarization layer;
patterning the planarization layer by using the mask pattern as an etching mask; and
patterning the conductive material layer, thereby forming an erase gate line between the first and second stacked structures and a first and a second word line, such that the first word line, the first stacked structure, the erase gate line, the second stacked structure and the second word line are arranged in this order along a direction parallel to a principal surface of the substrate, wherein:
the mask pattern includes a first mask pattern and a second mask pattern, and
the first mask pattern is formed above a region where the first word line is to be formed, and the second mask pattern is formed above a region where the second word line is to be formed.
2. The method of claim 1 , wherein the mask pattern as formed does not overlap the first and second stacked structures in plan view.
3. The method of claim 2 , wherein the first and second stacked structures and the mask pattern extend in a first direction and are arranged in parallel with each other.
4. The method of claim 1 , wherein no mask pattern is formed above a region between the first and second stacked structures where the erase gate line is to be formed.
5. The method of claim 1 , wherein:
at least one of the first and second word lines includes a protrusion, and
a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate.
6. The method of claim 1 , wherein:
each of the first and second stacked structures includes a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from the substrate, and
the second insulating layer includes a silicon oxide-silicon nitride-silicon oxide film.
7. The method of claim 6 , wherein:
at least one of the first and second word lines includes a protrusion, and
a height of the protrusion from the substrate is higher than a height of the third insulating layer from the substrate.
8. The method of claim 1 , wherein:
the planarization layer includes a bottom layer and an upper layer, and
the bottom layer is formed to cover the conductive material layer.
9. The method of claim 8 , wherein the bottom layer includes a dielectric material including silicon, oxygen and carbon.
10. A method of manufacturing a semiconductor device including a non-volatile memory area and a logic circuit area, the method comprising:
forming a first and a second stacked structure of a non-volatile memory over the non-volatile memory area of a substrate;
forming a conductive material layer over the first and second stacked structures and over the logic circuit area of the substrate;
forming a planarization layer over the conductive material layer;
forming a first mask pattern on the planarization layer over the non-volatile memory area and a second mask pattern on the planarization layer over the logic circuit area;
patterning the planarization layer by using the first and second mask patterns as an etching mask; and
patterning the conductive material layer, thereby forming an erase gate line between the first and second stacked structure and a first and a second word line in the non-volatile memory area such that the first word line, the first stacked structure, the erase gate line, the second stacked structure and the second word line are arranged in this order along a direction parallel to a principal surface of the substrate, and forming a gate pattern in the logic circuit area,
the first mask pattern includes a first-first mask pattern and a second-first mask pattern, and
the first-first mask pattern is formed above a region where the first word line is to be formed, and the second-first mask pattern is formed above a region where the second word line is to be formed.
11. The method of claim 10 , wherein the first mask pattern as formed does not overlap the first and second stacked structures in plan view.
12. The method of claim 11 , wherein the first and second stacked structures and the first mask pattern extend in a first direction and are arranged in parallel with each other.
13. The method of claim 10 , wherein no mask pattern is formed above a region between the first and second stacked structures, where the erase gate line is to be formed.
14. The method of claim 10 , wherein:
at least one of the first and second word lines includes a protrusion, and
a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate.
15. The method of claim 10 , wherein:
each of the first and second stacked structures includes a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from the substrate, and
the second insulating layer includes a silicon oxide-silicon nitride-silicon oxide film.
16. The method of claim 15 , wherein:
at least one of the first and second word lines includes a protrusion, and
a height of the protrusion from the substrate is higher than a height of the third insulating layer from the substrate.
17. The method of claim 10 , wherein:
the planarization layer includes a bottom layer and an upper layer, and
the bottom layer is formed to cover the conductive material layer.
18. A method of manufacturing a semiconductor device including a non-volatile memory area and a logic circuit area, the method comprising:
forming a first and a second stacked structure of a non-volatile memory over the non-volatile memory area of a substrate;
forming a polysilicon layer over the first and second stacked structures and over the logic circuit area of the substrate;
forming a planarization layer over the polysilicon layer;
forming a mask pattern on the planarization layer over the logic circuit area;
patterning the planarization layer by using the mask pattern as an etching mask; and
patterning the polysilicon layer, thereby forming a gate pattern in the logic circuit area, wherein:
the planarization layer includes a bottom layer and an upper layer thinner than the bottom layer, and
the bottom layer is formed to cover the polysilicon layer.