Semiconductor component that includes a clamping structure and method of manufacturing the semiconductor component
Embodiments include a method and structure to that provide a clamping structure in an integrated semiconductor device. In accordance with an embodiment, the method includes forming trenches in a semiconductor material and forming a shield electrode in a portion of at least one of the trenches. A clamping structure is formed adjacent to a trench. The clamping structure has an electrode that may be electrically connected to a source region of the integrated semiconductor device. In accordance with another embodiment, an impedance element is formed in a trench.
1. A method for suppressing charge injection in a semiconductor component, comprising:
providing a semiconductor material of a first conductivity type, a first concentration, and having a first major surface and a second major surface;
forming a first trench in the semiconductor material that extends from the first major surface into a first portion of the semiconductor material and a second trench in a second portion of the semiconductor material, the first trench having a first sidewall, a second sidewall, and a floor and the second trench having a first sidewall, a second sidewall, and a floor;
forming a shielded gate semiconductor device from a third portion of the semiconductor material and a portion of the first trench; and
forming a third trench in the semiconductor material that extends from the major surface into a fourth portion of the semiconductor material, the third trench having a first sidewall, a second sidewall, and a floor;
forming a first clamping structure in a fifth portion of the semiconductor material between the first trench and the third trench, wherein forming the third trench includes spacing the third trench away from the first trench so that a width of a region of the semiconductor material between the first trench and the third trench is set to prevent the region of the semiconductor material between the first trench and the third trench from fully depleting in response to avalanche breakdown occurring in the region of the semiconductor material between the first trench and the third trench.
2. The method of claim 1 , further including forming a first dopant region of a second conductivity type extending from the first major surface into the semiconductor material a first distance.
3. The method of claim 2 , wherein forming the first trench and the third trench forms a mesa structure from the semiconductor material between the first trench and the third trench, and further including:
forming a first dielectric material along the first sidewall, the second sidewall, and the floor of the first trench;
forming a second dielectric material along the first sidewall, the second sidewall, and the floor of the third trench;
forming a first shield electrode in the first trench, the first shield electrode adjacent the floor of the first trench;
forming a first electrically insulating material over the first shield electrode;
forming a first gate electrode of the shielded gate semiconductor device over the first electrically insulating material; and
forming a second shield electrode in the third trench and adjacent the floor of the third trench.
4. The method of claim 2 , further including:
forming a first dielectric material along the first sidewall, the second sidewall, and the floor of the first trench;
forming a second dielectric material along the first sidewall, the second sidewall, and the floor of the third trench;
forming a first shield electrode in the first trench, the first shield electrode adjacent the floor of the first trench;
forming a first electrically insulating material over the first shield electrode;
forming a first gate electrode of the shielded gate semiconductor device over the first electrically insulating material, wherein a breakdown voltage adjacent the first gate electrode is clamped to be lower than a breakdown voltage adjacent the first shield electrode; and
forming a second shield electrode in the third trench and adjacent the floor of the third trench.
5. The method of claim 2 , wherein forming the shielded gate semiconductor device further includes forming a second dopant region of the first conductivity type in the semiconductor material adjacent the first trench, the second dopant region extending a second distance from the first major surface into the semiconductor material, the second distance less than the first distance.
6. The method of claim 5 , wherein forming the first clamping structure between the first trench and the third trench includes:
forming a first clamping contact opening in the fifth portion of the semiconductor material between the first trench and the third trench, the first clamping contact opening extending a third distance into the semiconductor material, the third distance less than the first distance; and
forming a first clamping contact in the first clamping contact opening.
7. The method of claim 6 , further including forming a third dopant region of a second conductivity type in a portion of the semiconductor material exposed by the first clamping contact opening.
8. The method of claim 7 , wherein forming the first clamping contact in the first clamping contact opening includes:
forming a first barrier structure in the first clamping contact opening; and
forming an electrically conductive material over the first barrier structure.
9. The method of claim 8 , further including forming a second clamping structure in a sixth portion of the semiconductor material between the first clamping structure and the third trench.
10. The method of claim 9 , wherein forming the second clamping structure between the first clamping structure and the third trench includes:
forming a second clamping contact opening in a second portion of the semiconductor material between the first trench and the third trench, the second clamping contact opening extending the third distance into the semiconductor material; and
forming a second clamping contact in the second clamping contact opening.
11. The method of claim 8 , further including forming a fourth dopant region of the second conductivity type in a portion of the semiconductor material exposed by the second clamping contact opening.
12. The method of claim 8 , further including forming a fourth dopant region of the first conductivity type in a region of the semiconductor material between the first trench and the third trench.
13. A method for suppressing charge injection in a semiconductor component, comprising:
providing a semiconductor material of a first conductivity type, a first concentration, and having a first major surface and a second major surface;
forming first and second device trenches in first and second portions of the semiconductor material, respectively, wherein the first device trench extends from the first major surface into the first portion of the semiconductor material and has a first sidewall, a second sidewall, and a floor, and the second device trench extends from the first major surface into the second portion of the semiconductor material, and wherein the first device trench is separated from the second device trench by a first mesa structure having a first width;
forming first and second clamping trenches in third and fourth portions of the semiconductor material, respectively, wherein the first clamping trench extends from the first major surface into the third portion of the semiconductor material and has a first sidewall, a second sidewall, and a floor, and the second clamping trench extends from the first major surface into the fourth portion of the semiconductor material, and wherein the first clamping trench is separated from the second clamping trench by a second mesa structure having a second width; and wherein
the first width of the first mesa structure is configured so that the first mesa structure is fully depleted of charge carriers before avalanche breakdown occurs in the first mesa structure, and the second width of the second mesa structure is configured so that the second mesa structure is not fully depleted in response to avalanche breakdown occurring in the second mesa structure.
14. The method of claim 13 , further including configuring the first mesa structure and the second mesa structure so that avalanche breakdown occurs in the second mesa structure at a lower voltage than in the first mesa structure.
15. The method of claim 14 , further including forming the first device trench, the second device trench, the first clamping trench, and the second clamping trench so that the second width of the second mesa structure is at least 20 percent larger than the first width of the first mesa structure.
16. The method of claim 15 , further including:
forming a first shield electrode in a first portion of the first device trench;
forming a second shield electrode in a first portion of the second device trench;
forming a first transistor from a second portion of the first device trench and a first portion of the first mesa structure; and
forming a second transistor from a second portion of the second device trench and a second portion of the first mesa structure.
17. The method of claim 15 , further including forming a first clamping structure from the second mesa structure.
18. The method of claim 15 , wherein forming the first clamping structure includes forming an electrically conductive material in the first clamping trench and the second clamping trench.
19. A method for suppressing charge injection in a semiconductor component, comprising:
providing a semiconductor material of a first conductivity type and having first and second major surfaces;
forming a plurality of mesa structures from the semiconductor material of the first conductivity type, a first mesa structure of the plurality of mesa structures having a first width and a second mesa structure of the plurality of mesa structures having a second width;
forming a shielded gate semiconductor device from the first mesa structure of the plurality of mesa structures and a portion of a first trench adjacent the first mesa structure, wherein the shielded gate semiconductor device includes a first shielded gate structure between the first mesa structure and the second mesa structure;
forming a first clamping structure in the second mesa structure of the plurality of mesa structures; and
forming a first shield structure adjacent the second mesa structure, and wherein
the first width of the first mesa structure is configured so that the first mesa structure is fully depleted of charge carriers before avalanche breakdown occurs in the first mesa structure, and the second width of the second mesa structure is configured so that the second mesa structure is not fully depleted in response to avalanche breakdown occurring in the second mesa structure.
20. The method of claim 19 , wherein forming the first shielded gate structure comprises:
forming the first trench between the first mesa structure and the second mesa structure and a second trench adjacent the second mesa structure;
forming a first gate shield in a first portion of the first trench; and
forming a first gate electrode in a second portion of the first trench, the first gate electrode vertically spaced apart from the first gate shield by a first dielectric material; and wherein forming the first clamping structure comprises:
forming a first clamping contact opening in a first portion of the semiconductor material between the first trench and the second trench, the first clamping contact opening extending a first distance into the semiconductor material and having a width equal to at least half a width of the first mesa structure, the first clamping contact opening having a floor and sidewalls;
forming a first dopant region of a second conductivity type extending from the clamping contact opening into the semiconductor material;
forming a barrier structure on the floor and the sidewalls of the of the clamping contact opening; and
forming an electrically conductive material in the clamping opening.