Electronic device including a polycrystalline compound semiconductor layer and a process of forming the same
View Patent ↗An electronic device can include a substrate having a primary surface; a monocrystalline semiconductor film overlying the primary surface of the substrate; and a polycrystalline compound semiconductor layer adjacent to the monocrystalline semiconductor film. In an embodiment, the polycrystalline compound semiconductor layer has a dopant concentration at most 1×10 16 atoms/cm 3 , a donor concentration of greater than 1×10 17 donors/cm 3 , and is part of a contact of an electrode of a transistor. In another embodiment, the electronic device can further include an interconnect over the polycrystalline compound semiconductor layer, wherein a combination of the interconnect and polycrystalline compound semiconductor layer form an ohmic contact. In a further embodiment, a polycrystalline compound semiconductor layer can be adjacent to the monocrystalline semiconductor film, wherein an energy level of a conduction band of the polycrystalline compound semiconductor layer is lower than its Fermi energy level.
1. An electronic device comprising:
a substrate having a primary surface;
a monocrystalline semiconductor film overlying the primary surface of the substrate; and
a polycrystalline compound semiconductor layer adjacent to the monocrystalline semiconductor film, wherein the polycrystalline compound semiconductor layer has a dopant concentration of at most 1×10 16 atoms/cm 3 , a donor concentration of greater than 1×10 17 donors/cm 3 , and is a part of a contact of an electrode of a transistor.
2. The electronic device of claim 1 , wherein each of the monocrystalline semiconductor film and the polycrystalline compound semiconductor layer includes a III-V semiconductor material.
3. The electronic device of claim 1 , wherein the monocrystalline semiconductor film and the polycrystalline compound semiconductor layer include a same III-N semiconductor material.
4. The electronic device of claim 1 , wherein the polycrystalline compound semiconductor layer is undoped.
5. The electronic device of claim 1 , further comprising an interconnect, wherein a combination of the interconnect and polycrystalline compound semiconductor layer form an ohmic contact.
6. The electronic device of claim 1 , wherein the monocrystalline semiconductor film is a channel film of a transistor.
7. The electronic device of claim 6 , further comprising a barrier film overlying the channel film, wherein the barrier film has a different composition as compared to the channel film.
8. The electronic device of claim 7 , wherein the polycrystalline compound semiconductor layer is spaced apart from the channel film by at least a portion of the barrier layer.
9. The electronic device of claim 7 , wherein the polycrystalline compound semiconductor layer is no further than 70 nm away from the channel film.
10. The electronic device of claim 7 , wherein a portion of the polycrystalline compound semiconductor layer extends through the barrier film and contacts the channel film.
11. The electronic device of claim 7 , wherein the channel film is a GaN film, the polycrystalline compound semiconductor layer is a GaN layer, and the barrier film includes Al y Ga (1-y) N, wherein 0.05≦y≦0.3.
12. The electronic device of claim 11 , further comprising a gate electrode, wherein:
a first portion of the polycrystalline compound semiconductor layer is part of a source electrode;
a second portion of the polycrystalline compound semiconductor layer is part of a drain electrode; and
the channel film, the source, drain, and gate electrodes are parts of the transistor.
13. A process of forming an electronic device comprising:
forming a monocrystalline semiconductor film over a primary surface of a substrate;
forming a polycrystalline compound semiconductor layer over the monocrystalline semiconductor film, wherein the polycrystalline compound semiconductor layer has a dopant concentration no greater than 1×10 16 atoms/cm 3 and a donor concentration of greater than 1×10 17 donors/cm 3 , and
forming an interconnect over the polycrystalline compound semiconductor layer, wherein a combination of the interconnect and polycrystalline compound semiconductor layer form an ohmic contact.
14. The process of claim 13 , wherein the monocrystalline semiconductor film and the polycrystalline compound semiconductor layer include a III-N semiconductor material.
15. The process of claim 14 , wherein each of the monocrystalline semiconductor film and the polycrystalline compound semiconductor layer includes GaN.
16. The process of claim 15 , further comprising:
forming a barrier film over the monocrystalline semiconductor film, wherein the barrier film includes Al y Ga (1-y) N, wherein 0.05≦y≦0.3; and
forming a gate electrode over the barrier film.
17. The process of claim 16 , wherein:
portions of the polycrystalline compound semiconductor layer comprise a source electrode and a drain electrode, and
the channel film, the source, drain, and gate electrodes are parts of a same transistor.
18. The process of claim 13 , wherein forming the polycrystalline compound semiconductor layer is performed at a temperature no greater than 900° C.
19. The process of claim 13 , wherein the polycrystalline compound semiconductor layer is not formed nor exposed to a temperature of at least 1000° C. during any part of forming the electronic device.