Chip scale package and related methods
View Patent ↗Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
1. A semiconductor package comprising:
a die coupled to a glass lid;
one or more inner walls comprising a first material coupled to the die;
an outer wall comprising a second material coupled to the die; and
a glass lid coupled to the die at the one or more inner walls and at the outer wall;
wherein the outer wall is located at the edge of the die and the glass lid and the one or more inner walls are located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and
wherein a modulus of the first material is lower than a modulus of the second material.
2. The semiconductor package of claim 1 , wherein a maximum cavity wall stress on the outer wall and on the one or more inner walls is less than 40 MPa.
3. The semiconductor package of claim 1 , wherein the semiconductor package is capable of passing a moisture sensitivity level (MSL) 1 test.
4. The semiconductor package of claim 1 , wherein the first material is a dry film and the second material is a solder mask.