Techniques for delegating data processing to a cooperative memory controller
Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.
1. A memory controller to control flash memory, the flash memory having a plurality of storage locations disposed within structural elements of the flash memory, the memory controller comprising:
circuitry to control the storage of data in the flash memory in response to a request from a host, the request including a first command, the first command to cause the memory controller to store first data within a first one of the structural elements in the flash memory and to generate second data, the second data being redundancy information which is dependent on the first data; and
a random access memory to receive the second data in association with the first command and to store the second data at an address in the random access memory;
wherein the memory controller is to receive a second command from the host, the second command specifying the address in the random access memory and a destination address within the flash memory, the specified destination address being mapped in advance to a second one of the structural elements to the exclusion of others of the structural elements such that the host selects the second one of the structural elements, the memory controller to responsively transfer the second data from the address in the random access memory to the second one of the structural elements in a manner not requiring intervening transfer of the second data from the random access memory to the host.
2. The memory controller of claim 1 , wherein:
the memory controller further comprises
processing circuitry responsive to the first command to generate the second data, and
transmit circuitry to transmit information to the host in association with generation of the second data; and
the second command is to be transmitted by the host to the memory controller responsive to the information transmitted to the host by the transmit circuitry.
3. The memory controller of claim 2 , wherein:
the information to be transmitted to the host comprises the address in the random access memory.
4. The memory controller of claim 1 , wherein:
the memory controller further comprises a register to store an indication of operating mode;
when the indication represents a first operating mode, the processing circuitry is to be operated so as to automatically generate the second data in response to a write of the first data; and
when the indication represents a second operating mode, the processing circuitry is not to be operated, and the memory controller is not to automatically generate redundancy information in response to a write of the first data.
5. The memory controller of claim 1 , wherein:
the first command is a write command from the host, the write command being accompanied by the first data, to cause the memory controller to write the first data into the flash memory; and
the processing circuitry is to generate the second data as error correction information for the first data, the error correction information sufficient to permit the recovery of the first data notwithstanding an error in the first data when retrieved from the first one of the structural elements.
6. The memory controller of claim 1 , wherein:
the first command is to convey a logical address operand of the first command and the first data;
the processing circuitry is to generate the second data dependent on the first data, provided that the logical address operand corresponds to a predetermined address range; and
the memory controller is to transfer the first data to the flash memory and the processing circuitry is not to generate the second data if the logical address operand does not correspond to the predetermined address range.
7. The memory controller of claim 1 , wherein:
the second data represents a quantum of data which is smaller than a minimum size write unit in the flash memory, and the memory controller is to accumulate said second data and third data in the random access memory, said second command being a command to transfer the second data and the third data to the second one of the structural elements as a write of at least a minimum size write unit of data into the flash memory.
8. The memory controller of claim 1 , wherein:
the memory controller is to receive a third command in between receipt of the first command and the second command;
the memory controller is to, in response to the third command, access a storage location in the specified one of the structural elements;
the second command is to be executed by the memory controller only after completion of the third command by the memory controller.
9. The memory controller of claim 1 , wherein the structural elements comprise respective erase units in the flash memory.
10. The memory controller of claim 1 , wherein the structural elements comprise respective memory arrays in the flash memory.
11. The memory controller of claim 1 , wherein the structural elements comprise respective channels in the flash memory.
12. The memory controller of claim 1 , further comprising circuitry to translate a logical address associated with the data and provided with at least one of the first command or the second command, to a physical address in the specified one of the structural elements.
13. The memory controller of claim 1 , embodied as a memory controller integrated circuit.
14. A memory device, comprising:
flash memory having a plurality of storage locations disposed within structural elements of the flash memory; and
a memory controller comprising
circuitry to control the storage of data in the flash memory in response to a request from a host, the request including a first command, the first command to cause the memory controller to store first data within a first one of the structural elements in the flash memory and to generate second data, the second data being redundancy information which is dependent on the first data, and
a random access memory to receive the second data in association with the first command and to store the second data at an address in the random access memory;
wherein the memory controller is to receive a second command from the host, the second command specifying the address in the random access memory and a destination address within the flash memory, the specified destination address being mapped in advance to a second one of the structural elements to the exclusion of others of the structural elements, such that the host selects the second one of the structural elements, the memory controller to responsively transfer the second data from the address in the random access memory to the one of the structural elements in a manner not requiring intervening transfer of the second data from the random access memory to the host.
15. The memory device of claim 14 , wherein:
the memory controller further comprises
processing circuitry responsive to the first command to generate the second data, and
transmit circuitry to transmit information to the host in association with generation of the second data; and
the second command is to be transmitted by the host to the memory controller responsive to the information transmitted to the host by the transmit circuitry.
16. The memory device of claim 14 , wherein:
the first command is a write command from the host, the write command being accompanied by the first data, to cause the memory controller to write the first data into the flash memory; and
the processing circuitry is to generate the second data as error correction information for the first data, the error correction information sufficient to permit the recovery of the first data notwithstanding an error in the first data when retrieved from the first one of the structural elements.
17. The memory device of claim 14 , wherein the structural elements comprise one of respective erase units in the flash memory, respective dies in the flash memory, or respective channels in the flash memory.
18. The memory device of claim 14 , wherein:
the memory controller further comprises a register to store an indication of operating mode;
when the indication represents a first operating mode, the processing circuitry is to be operated so as to automatically generate the second data in response to a write of the first data; and
when the indication represents a second operating mode, the processing circuitry is not to be operated, and the memory controller is not to automatically generate redundancy information in response to a write of the first data.
19. The memory device of claim 14 , wherein:
the information to be transmitted to the host comprises the address in the random access memory.
20. The memory device of claim 14 , wherein:
the first command is to convey a logical address operand of the first command and the first data;
the processing circuitry is to generate the second data dependent on the first data, provided that the logical address operand corresponds to a predetermined address range; and
the memory controller is to transfer the first data to the flash memory and the processing circuitry is not to generate the second data if the logical address operand does not correspond to the predetermined address range.
21. The memory device of claim 14 , wherein:
the second data represents a quantum of data which is smaller than a minimum size write unit in the flash memory, and the memory controller is to accumulate said second data and third data in the random access memory, said second command being a command to transfer the second data and the third data to the second one of the structural elements as a write of at least a minimum size write unit of data into the flash memory.
22. The memory device of claim 14 , wherein:
the memory controller is to receive a third command in between receipt of the first command and the second command;
the memory controller is to, in response to the third command, access a storage location in the specified one of the structural elements;
the second command is to be executed by the memory controller only after completion of the third command by the memory controller.
23. The memory device of claim 14 , wherein the structural elements comprise respective memory arrays in the flash memory.