FinFET-based ESD devices and methods for forming the same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
1. A semiconductor device comprising:
a first array of FinFETs over a semiconductor substrate, each one of the FinFETs within the first array of FinFETs comprising:
a plurality of semiconductor fins on semiconductor strips on the semiconductor substrate, the semiconductor fins being parallel to each other;
a gate stack over the semiconductor fins;
a drain epitaxy semiconductor region disposed laterally from a side of the gate stack and on the semiconductor strips, wherein the drain epitaxy semiconductor region further comprises:
a first portion proximate the gate stack; and
second portions distally disposed from the gate stack relative to the first portion, a thickness of the first portion being greater than a thickness of the second portions; and
a first dielectric layer over the substrate, the first dielectric layer having a first metal layer, wherein the first metal layer is in electrical connection with multiple ones of the FinFETs within the first array of FinFETs.
2. The semiconductor device of claim 1 , further comprising a second dielectric layer between the substrate and the first metal layer, wherein the second dielectric layer comprises a second metal layer.
3. The semiconductor device of claim 2 , wherein the first metal layer has a larger width than the second metal layer.
4. The semiconductor device of claim 2 , wherein the first metal layer has a larger thickness than the second metal layer.
5. The semiconductor device of claim 2 , further comprising first vias extending from the first metal layer and second vias extending from the second metal layer, wherein the first vias have a larger width than the second vias.
6. The semiconductor device of claim 1 , wherein the first metal layer is a bottom metal layer.
7. A semiconductor device comprising:
a first fin of semiconductor material over a semiconductor substrate;
a second fin of semiconductor material over the semiconductor substrate:
a first isolation region between the first fin and the second fin;
a first gate electrode over the first fin and the second fin;
a second gate electrode over the first fin and the second fin;
a drain region extending from the first gate electrode to the second gate electrode and extending from the first fin to the second fin; and
a depression within the drain region, wherein the depression has a curved surface and exposes the first isolation region.
8. The semiconductor device of claim 7 , further comprising:
a pick-up device encircling a first region of a semiconductor substrate in a top-down view; and
an electrostatic discharge device located within the first region, wherein the electrostatic discharge device comprises the first fin.
9. The semiconductor device of claim 8 , wherein the pick-up device comprises one or more highly doped wells with a first conductivity and wherein the semiconductor substrate has the first conductivity, further comprising at least one dummy gate structure overlying the one or more highly doped wells.
10. The semiconductor device of claim 8 , further comprising a first metallization layer over the semiconductor substrate, wherein the first metallization layer comprises a conductive region that encircles the first region in a top down view.
11. The semiconductor device of claim 10 , further comprising contacts electrically connecting the conductive region with the pick-up device.
12. The semiconductor device of claim 10 , further comprising a second metallization layer between the first metallization layer and the semiconductor substrate, wherein the second metallization layer comprises a conductive line.
13. The semiconductor device of claim 12 , further comprising first vias extending from the first metallization layer through the second metallization layer.
14. The semiconductor device of claim 13 , further comprising second vias extending from the second metallization layer, wherein the first vias have a larger width than the second vias.
15. A semiconductor device comprising:
a semiconductor fin over a substrate;
a first gate stack over the semiconductor fin;
a second gate stack over the semiconductor fin; and
a drain region extending from the first gate stack to the second gate stack, wherein the drain region has a merged drain epitaxy region and a non-merged drain epitaxy region.
16. The semiconductor device of claim 15 , further comprising a first driving transistor with a first drain coupled to a node, wherein the semiconductor fin is part of an electrostatic discharge device coupled to the node.
17. The semiconductor device of claim 16 , wherein the first driving transistor is an output driver circuit.
18. The semiconductor device of claim 16 , wherein the electrostatic discharge device is incorporated into a driving circuit with the first driving transistor.
19. The semiconductor device of claim 16 , further comprising a second driving transistor coupled to the node.
20. The semiconductor device of claim 16 , where the electrostatic discharge device is a standalone device.