Programmable decoupling capacitance of configurable logic circuitry and method of operating same
An integrated circuit comprising at least one logic tile including a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output and a plurality of selection inputs to receive selection signals to determine whether an input of the plurality of inputs is connected to the output. The logic tile further includes (i) at least one inactive multiplexer having an output that is inactive in the network configuration and/or (ii) at least one static multiplexer receiving static selection signals, wherein during operation of the integrated circuit, the selection inputs of the inactive and/or the static multiplexer receive selection signals responsively connect (whether directly or indirectly) two or more inputs of the inactive and/or the static multiplexer to the output of the inactive multiplexer.
1. An integrated circuit comprising:
control circuitry;
one or more logic tiles, wherein at least one logic tile is connected to the control circuitry and includes:
a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output, and a plurality of selection inputs to receive selection signals to determine whether an input of the multiplexer is connected to the output of that multiplexer;
an inactive multiplexer including a plurality of inputs, an output that is inactive in the network configuration, and a plurality of selection inputs to receive selection signals to determine whether an input of the inactive multiplexer is connected to the output of the inactive multiplexer; and
wherein, in operation of the integrated circuit, the selection inputs of the inactive multiplexer receive selection signals to concurrently connect two or more inputs of the inactive multiplexer to the output of the inactive multiplexer.
2. The integrated circuit of claim 1 wherein at least one input of the inactive multiplexer is connected to an active multiplexer having an output that is active in the network configuration.
3. The integrated circuit of claim 1 wherein the inactive multiplexer includes a plurality of transistors which, in response to the selection signals, concurrently connect the two or more inputs of the inactive multiplexer to the output of the inactive multiplexer.
4. The integrated circuit of claim 3 wherein parasitic capacitances of the plurality of transistors are included into a decoupling path of the integrated circuit in response to coupling two or more inputs of the inactive multiplexer to the output of the inactive multiplexer.
5. The integrated circuit of claim 1 wherein each of the two or more inputs of the inactive multiplexer is connected to a data storage element, an input pin, a lookup table, and/or an output of another multiplexer of the plurality of multiplexers.
6. The integrated circuit of claim 1 wherein the control circuitry identifies the inactive multiplexer and programs the inactive multiplexer via selection signals applied at the selection inputs of the inactive multiplexer.
7. The integrated circuit of claim 1 wherein the control circuitry identifies the inactive multiplexer and programs the inactive multiplexer via the selection signals applied at the selection inputs of the inactive multiplexer wherein, in response, a predetermined number of inputs of the inactive multiplexer are concurrently connected to the output of the inactive multiplexer.
8. The integrated circuit of claim 7 wherein a polarity of the signals applied to the inputs of the predetermined number of inputs is identical.
9. The integrated circuit of claim 7 wherein the predetermined number of inputs is greater than or equal to two and less than the total number of inputs of the inactive multiplexer.
10. The integrated circuit of claim 7 wherein the predetermined number of inputs is less than the total number of inputs of the inactive multiplexer.
11. An integrated circuit comprising:
control circuitry;
one or more logic tiles, wherein at least one logic tile is connected to the control circuitry and includes:
a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output, and a plurality of selection inputs to receive selection signals to determine whether an input of the multiplexer is connected to the output of that multiplexer;
an inactive multiplexer including a plurality of inputs, an output that is inactive in the network configuration, and a plurality of selection inputs to receive selection signals to determine whether an input of the multiplexer is connected to the output of the inactive multiplexer;
a static multiplexer including a plurality of inputs, an output that is interconnected into the network configuration, and a plurality of selection inputs; and
wherein, in operation of the integrated circuit,
the selection inputs of the inactive multiplexer receive selection signals which responsively connect two or more inputs of the inactive multiplexer to the output of the inactive multiplexer, and
the selection inputs of the static multiplexer receive selection signals that are static and responsively and concurrently connect two or more inputs of the static multiplexer to the output of the static multiplexer.
12. The integrated circuit of claim 11 wherein the control circuitry identifies the inactive multiplexer and the static multiplexer and programs the inactive multiplexer and the static multiplexer via the selection signals applied to the respective selection inputs wherein, in response,
the two or more inputs of the inactive multiplexer are concurrently connected to the output of the inactive multiplexer, and
the two or more inputs of the static multiplexer are concurrently connected to the output of the static multiplexer.
13. An integrated circuit comprising:
control circuitry;
one or more logic tiles, wherein at least one logic tile is connected to the control circuitry and includes:
a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output, and a plurality of selection inputs to receive selection signals to determine whether an input of the multiplexer is connected to the output of the multiplexer;
a static multiplexer including a plurality of inputs, an output that is interconnected into the network configuration and a plurality of selection inputs; and
wherein, in operation of the integrated circuit, the selection inputs of the static multiplexer receive selection signals that are static and concurrently connect two or more inputs of the static multiplexer to the output of the static multiplexer.
14. The integrated circuit of claim 13 wherein the input signals received at the two or more inputs of the static multiplexer are (i) constant and (ii) an identical polarity.
15. The integrated circuit of claim 13 wherein the static multiplexer includes a plurality of transistors which, in response to the selection signals, concurrently connect the two or more inputs of the static multiplexer to the output of the static multiplexer.
16. The integrated circuit of claim 15 wherein parasitic capacitances of the plurality of transistors are included into a decoupling path of the integrated circuit in response to coupling two or more inputs of the static multiplexer to the output of the static multiplexer.
17. The integrated circuit of claim 13 wherein the control circuitry identifies the static multiplexer and programs the static multiplexer via selection signals applied to the plurality of selection inputs of the static multiplexer.
18. The integrated circuit of claim 13 wherein the control circuitry identifies the static multiplexer and programs the static multiplexer via the selection signals wherein, in response, a predetermined number of inputs of the static multiplexer are concurrently connected to the output of the static multiplexer.
19. The integrated circuit of claim 18 wherein the input signals applied to the inputs of the predetermined number of inputs of the static multiplexer are (i) constant and (ii) an identical polarity.
20. The integrated circuit of claim 18 wherein the predetermined number of inputs is less than the total number of inputs of the static multiplexer.