Patent Assignment
Reel/Frame 069409/0035
Assignment of Assignor's Interest
Recorded: 2024-11-21
Pages: 17
Assignor
FLEX LOGIX TECHNOLOGIES, INC.
Executed: 2024-11-05
Assignee
ANALOG DEVICES, INC.
ONE ANALOG WAY, WILMINGTON, MASSACHUSETTS, 01887
Covered Properties
(70)
Coarse Floating Point Accumulator Circuit, and MAC Processing Pipelines including Same
Patent:
12,282,748 →
Application:
17/313,037 →
Configurable MAC Pipelines for Finite-Impulse-Response Filtering, and Methods of Operating Same
Multiplier Circuit Array, MAC and MAC Pipeline including Same, and Methods of Configuring Same
Application:
17/511,798 →
Publication:
US 2022/0171604
MAC Processing Pipeline having Activation Circuitry, and Methods of Operating Same
Application:
17/577,454 →
Publication:
US 2022/0244917
MAC Processing Pipelines, Circuitry to Configure Same, and Methods of Operating Same
Application:
17/683,284 →
Publication:
US 2022/0283779
Modular Field Programmable Gate Array, and Method of Configuring and Operating the Same
Patent:
50,504 →
Application:
17/804,945 →
Multiplier-Accumulator Circuitry, and Processing Pipeline including Same
Multiply-Accumulate with Broadcast Data
Application:
18/080,673 →
Publication:
US 2023/0185531
Multiply-Accumulate with Variable Floating Point Precision
Application:
18/088,153 →
Publication:
US 2023/0131459
Broadcast Data, Shared Weight Multiply-Accumulate
Application:
18/111,846 →
Publication:
US 2023/0266968
Broadcast Data Multiply-Accumulate with Shared Unload
Application:
18/144,288 →
Publication:
US 2023/0359437
Multiply-Accumulate Pipelines for Finite Impulse Response Filtering
Application:
18/215,993 →
Publication:
US 2024/0004612
Single-Weight-Multiple-Data Multiply-Accumulate with Winograd Layers
Application:
18/371,228 →
Publication:
US 2024/0111491
Single-Weight-Multiple-Data Matrix Multiply
Application:
18/371,247 →
Publication:
US 2024/0104165
Multiply-Accumulate with Configurable Conversion Between Normalized and Non-Normalized Floating-Point Formats
Application:
18/373,453 →
Publication:
US 2024/0111492
Multiply-Accumulate Engine with Non-Normalized Floating-Point Accumulator
Application:
18/373,468 →
Publication:
US 2024/0103808
Extreme-Throughput Fast-Fourier-Transform (FFT) Via Multi-Stage Tensor Processing
Application:
18/745,051 →
Publication:
US 2024/0419758
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
Patent:
9,543,958 →
Application:
15/015,057 →
Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
Patent:
9,786,361 →
Application:
15/213,933 →
Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network
Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network
Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same
FPGA having a Virtual Array of Logic Tiles, and Method of Configuring and Operating Same
FPGA having Programmable Powered-Up/Powered-Down Logic Tiles, and Method of Configuring and Operating Same
Test Circuitry and Techniques for Logic Tiles of FPGA
Patent:
10,523,209 →
Application:
16/186,882 →
Integrated Circuit Including an Array of Logic Tiles, Each Logic Tile Including a Configurable Switch Interconnect Network
Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
One-Hot-Bit Multiplexer Control Circuitry and Technique
Patent:
10,684,975 →
Application:
15/798,224 →
Modular Field Programmable Gate Array, and Method of Configuring and Operating Same
Patent:
10,686,447 →
Application:
16/374,735 →
Clock Architecture, including Clock Mesh Fabric for FPGA, and Method of Operating Same
Multiplier-Accumulator Circuit, Logic Tile Architecture for Multiply-Accumulate, and IC including Logic Tile Array
Programmable/Configurable Logic Circuitry, Control Circuitry and Method of Dynamic Context Switching
Patent:
10,775,433 →
Application:
16/369,809 →
Reconfigurable Data Processing Pipeline, and Method of Operating Same
Patent:
10,778,228 →
Application:
16/661,217 →
Process of Routing Tile-to-Tile Interconnects of an Fpga, and Method of Manufacturing an Fpga
Patent:
10,855,284 →
Application:
16/579,766 →
FPGA Implementing Partial Datapath Processing, and Method of Operating Same
Patent:
10,867,096 →
Application:
16/659,233 →
Test Circuitry and Techniques for Logic Tiles of FPGA
Multiplier-Accumulator Circuitry, and Processing Pipeline including Same
Multiplier-Accumulator Circuitry having Processing Pipelines and Methods of Operating Same
Process of Routing Tile-to-Tile Interconnects of an FPGA, and Method of Manufacturing an FPGA
IC including Logic Tile, having Reconfigurable MAC Pipeline, and Reconfigurable Memory
Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
Test Circuitry and Techniques for Logic Tiles of FPGA
MAC Processing Pipelines, Circuitry to Control and Configure Same, and Methods of Operating Same
Mac Processing Pipeline Having Conversion Circuitry, and Methods of Operating Same
Multiplier-Accumulator Circuitry, and Processing Pipeline Including Same
MAC Processing Pipelines having Programmable Granularity, and Methods of Operating Same
Multiplier-Accumulator Circuitry having Processing Pipelines and Methods of Operating Same
Ic Including Logic Tile, Having Reconfigurable Mac Pipeline, and Reconfigurable Memory
Logarithmic Addition-Accumulator Circuitry, Processing Pipeline including Same, and Methods of Operation
MAC Processing Pipelines, Circuitry to Control and Configure Same, and Methods of Operating Same
Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
Process of Routing Tile-to-Tile Interconnects of an FPGA, and Method of Manufacturing an FPGA
Multiplier-Accumulator Processing Pipeline using Filter Weights having Gaussian Floating Point Data Format
Patent:
11,960,856 →
Application:
17/140,169 →
Multiplier-Accumulator Processing Pipelines and Processing Component, and Methods of Operating Same
MAC Processing Pipeline having Conversion Circuitry, and Methods of Operating Same
MAC Processing Pipeline using Filter Weights having Enhanced Dynamic Range, and Methods of Operating Same
Power-up Switch-Interconnect Configuration
Patent:
12,119,819 →
Application:
18/078,033 →
Broadcast Data, Shared Weight Multiply-Accumulate
PCT:
PCT/US2023/013435 ↗
Extreme-Throughput Fast-Fourier-Transform (Fft) via Multi-Stage Tensor Processing
PCT:
PCT/US2024/034285 ↗
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 26, 2015
From: WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 035782/0078 →
Assignment of Assignor's Interest
Feb 29, 2016
From: WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 037961/0382 →
Assignment of Assignor's Interest
Feb 29, 2016
From: WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 037957/0332 →
Assignment of Assignor's Interest
May 15, 2021
From: WARE, FREDERICK A; WANG, CHENG C
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 056252/0975 →
Assignment of Assignor's Interest
Aug 20, 2021
From: WARE, FREDERICK A; WANG, CHENG C
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 057238/0601 →
Assignment of Assignor's Interest
Jan 10, 2022
From: WARE, FREDERICK A; WANG, CHENG C
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 058589/0475 →
Assignment of Assignor's Interest
Jan 28, 2022
From: WARE, FREDERICK A; WANG, CHENG C
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 058802/0449 →
Assignment of Assignor's Interest
Mar 31, 2022
From: WARE, FREDERICK A; WANG, CHENG C
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 059458/0396 →
Assignment of Assignor's Interest
Dec 14, 2022
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 062084/0072 →
Assignment of Assignor's Interest
Apr 26, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 063446/0749 →
Assignment of Assignor's Interest
Jun 8, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 063897/0837 →
Assignment of Assignor's Interest
Jul 14, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 064263/0610 →
Assignment of Assignor's Interest
Dec 11, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 065827/0463 →
Assignment of Assignor's Interest
Dec 11, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 065827/0272 →
Assignment of Assignor's Interest
Dec 11, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 065827/0715 →
Assignment of Assignor's Interest
Dec 11, 2023
From: WARE, FREDERICK A.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 065827/0569 →
Corrective Assignment to Correct the Omission Second Inventor's Name Previously Recorded at Reel: 065827 Frame: 0569. Assignor(S) Hereby Confirms the Assignment .
Dec 13, 2023
From: WARE, FREDERICK A.; WANG, CHENG C.
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 066144/0065 →
Assignment of Assignor's Interest
Jun 25, 2024
From: WARE, FREDERICK A.; WANG, CHENG C.; JARIWALA, NIKEN
To: FLEX LOGIX TECHNOLOGIES, INC.
Reel/Frame 067833/0006 →