IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
An integrated circuit including configurable multiplier-accumulator circuitry, wherein, during processing operations, a plurality of the multiplier-accumulator circuits are serially connected into pipelines to perform concatenated multiply and accumulate operations. The integrated circuit includes a first memory and a second memory, and a switch interconnect network, including configurable multiplexers arranged in a plurality of switch matrices. The first and second memories are configurable as either a dedicated read memory or a dedicated write memory and connected to a given pipeline, via the switch interconnect network, during a processing operation performed thereby; wherein, during a first processing operations, the first memory is dedicated to write data to a first pipeline and the second memory is dedicated to read data therefrom and, during a second processing operation, the first memory is dedicated to read data from a second pipeline and the second memory is dedicated to write data thereto.
1. An integrated circuit comprising:
multiplier-accumulator circuitry, configurable into a plurality of linear pipelines, to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes:
a multiplier to multiply first data by weight data and generate product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data, and
wherein the plurality of multiplier-accumulator circuits are configurable to form a plurality of linear MAC pipelines including a first linear MAC pipeline and a second linear MAC pipeline;
first memory, coupled to the multiplier-accumulator circuitry;
second memory, coupled to the multiplier-accumulator circuitry;
weight memory to store weight data and to output the weight data to the multiplier of each multiplier-accumulator circuit;
wherein, during a first data processing operation, the first linear MAC pipeline is configured to perform a plurality of multiply and accumulate operations of the first data processing operation, and wherein:
during the first data processing operation (i) the first memory is coupled to the first linear MAC pipeline to output data to the first linear MAC pipeline, and (ii) the second memory is coupled to store data from the first linear MAC pipeline, and wherein, during the first data processing operation, the first memory is configured to output data to the first MAC pipeline and the second memory is configured to store data from the first MAC pipeline; and
wherein, during a second data processing operation, the second linear MAC pipeline is configured to perform a plurality of multiply and accumulate operations of the second data processing operation, and wherein:
during the second data processing operation (i) the first memory is coupled to the second linear MAC pipeline to store data from the second linear MAC pipeline, and (ii) the second memory is coupled to the second linear MAC pipeline to output data to the second linear MAC pipeline, and wherein, during the second data processing operation, the first memory is configured to store data from the second linear MAC pipeline and the second memory is configured to output data to the second MAC pipeline.
2. The integrated circuit of claim 1 further including:
configurable interface circuitry coupled to the plurality of multiplier-accumulator circuits of the first linear MAC pipeline wherein the configurable interface circuitry includes a plurality of multiplexers that are configurable to couple an input of the first linear MAC pipeline to the first memory and an output of the first linear MAC pipeline to the second memory.
3. The integrated circuit of claim 2 wherein:
one or more multiplexers of the plurality of the multiplexers of the configurable interface circuitry is/are configurable to connect a third plurality of multiplier-accumulator circuits to a fourth plurality of multiplier-accumulator circuits to form the second linear MAC pipeline, and
one or more multiplexers of the plurality of the multiplexers of the configurable interface circuitry is/are further configurable to couple an input of the second linear MAC pipeline to the second memory and an output of the second linear MAC pipeline to the first memory during the second data processing operation.
4. The integrated circuit of claim 1 wherein:
during the first data processing operation, the first memory is configured to only output data and the second memory is configured to only store data;
during the second data processing operation, the first memory is configured to only store data and the second memory is configured to only output data.
5. The integrated circuit of claim 1 further including:
a switch interconnect network coupled to the first memory and the plurality of multiplier-accumulator circuits, wherein the switch interconnect network is configurable to couple an input of the first linear MAC pipeline to the first memory during the first data processing operation.
6. The integrated circuit of claim 5 wherein:
the switch interconnect network is further configurable to connect an output of the first linear MAC pipeline to the second memory during the first data processing operation.
7. The integrated circuit of claim 5 wherein:
the switch interconnect network is further configurable, during the second data processing operation, to connect an input of the second linear MAC pipeline to the second memory and output of the second linear MAC pipeline to the first memory.
8. The integrated circuit of claim 1 wherein:
at least a plurality of multiplier-accumulator circuits of the first linear MAC pipeline are different from a plurality of multiplier-accumulator circuits of the second linear MAC pipeline.
9. An integrated circuit comprising:
multiplier-accumulator circuitry, configurable into a plurality of linear pipelines, to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes:
a multiplier to multiply first data by weight data and generate product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data, and
wherein the plurality of multiplier-accumulator circuits are configurable to form a plurality of linear MAC pipelines including a first linear MAC pipeline and a second linear MAC pipeline;
first memory coupled to the multiplier-accumulator circuitry;
second memory coupled to the multiplier-accumulator circuitry;
weight memory to store weight data and to output the weight data to the multiplier of each multiplier-accumulator circuit;
wherein, during a first data processing operation, the first linear MAC pipeline is configurable to perform a plurality of multiply and accumulate operations of the first data processing operation, and wherein:
during the first data processing operation (i) the first memory is coupled to the first linear MAC pipeline to output data to the first linear MAC pipeline, and (ii) the second memory is coupled to store data from the first linear MAC pipeline, and wherein, during the first data processing operation, the first memory is configured to output data to the first MAC pipeline and the second memory is configured to store data from the first MAC pipeline; and
wherein, during a second data processing operation, the second linear MAC pipeline is configurable to perform a plurality of multiply and accumulate operations of the second data processing operation, and wherein:
during the second data processing operation the second memory is coupled to the second linear MAC pipeline to output data to the second linear MAC pipeline, and wherein, during the second data processing operation, the second memory is dedicated to output data including to the second MAC pipeline.
10. The integrated circuit of claim 9 wherein:
the data output from the second memory to the second linear MAC pipeline during the second data processing operation includes the data that were input from the first linear MAC pipeline during the first data processing operation.
11. The integrated circuit of claim 9 further including:
configurable interface circuitry coupled to the plurality of multiplier-accumulator circuits of the first linear MAC pipeline wherein the configurable interface circuitry includes a plurality of multiplexers that are configurable to couple an input of the first linear MAC pipeline to the first memory and an output of the first linear MAC pipeline to the second memory.
12. The integrated circuit of claim 11 wherein:
one or more multiplexers of the plurality of the multiplexers of the configurable interface circuitry is/are configurable to connect a first plurality of interconnected multiplier-accumulator circuits to a second plurality of interconnected multiplier-accumulator circuits to form the first linear MAC pipeline.
13. The integrated circuit of claim 11 wherein:
one or more multiplexers of the plurality of the multiplexers of the configurable interface circuitry is/are configurable to connect a third plurality of multiplier-accumulator circuits to a fourth plurality of multiplier-accumulator circuits to form the second linear MAC pipeline, and
one or more multiplexers of the plurality of the multiplexers of the configurable interface circuitry is/are further configurable to couple an input of the second linear MAC pipeline to the second memory during the second data processing operation.
14. The integrated circuit of claim 9 further including:
a switch interconnect network coupled to the first memory and the plurality of multiplier-accumulator circuits, wherein the switch interconnect network is configurable to couple an input of the first linear MAC pipeline to the first memory during the first data processing operation.
15. The integrated circuit of claim 14 wherein:
the switch interconnect network is further configurable to connect an output of the first linear MAC pipeline to the second memory during the first data processing operation.
16. The integrated circuit of claim 14 wherein:
the switch interconnect network is further configurable, during the second data processing operation, to connect an input of the second linear MAC pipeline to the second memory.
17. The integrated circuit of claim 9 wherein:
at least a plurality of multiplier-accumulator circuits of the first linear MAC pipeline are different from a plurality of multiplier-accumulator circuits of the second linear MAC pipeline.
18. An integrated circuit comprising:
multiplier-accumulator circuitry, configurable into a plurality of linear pipelines, to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes:
a multiplier to multiply first data by weight data and generate product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data, and
wherein the plurality of multiplier-accumulator circuits are configurable to form a plurality of linear MAC pipelines including a first plurality of linear MAC pipelines and a second plurality of linear MAC pipelines;
first memory coupled to the multiplier-accumulator circuitry;
second memory coupled to the multiplier-accumulator circuitry;
wherein, in a first configuration, the first plurality of linear MAC pipelines are configurable to perform a plurality of multiply and accumulate operations, and wherein:
in the first configuration, (i) the first memory is coupled to the first plurality of linear MAC pipelines to output data thereto, and (ii) the second memory is coupled to the first plurality of linear MAC pipelines to store data therefrom, and wherein, in the first configuration, the first memory is configured to only output data and the second memory is configured to only store data; and
wherein, in a second configuration, the second plurality of linear MAC pipelines are configurable to perform a plurality of multiply and accumulate operations, and wherein:
in the second configuration, the second memory is coupled to the second plurality of linear MAC pipelines to output data thereto, and wherein, in the second configuration, the second memory is configured to only output data.
19. The integrated circuit of claim 18 further including:
configurable interface circuitry coupled to the plurality of multiplier-accumulator circuits of the first plurality of linear MAC pipelines wherein the configurable interface circuitry includes a plurality of multiplexers that are configurable to couple inputs of the first plurality of linear MAC pipelines to the first memory and outputs of the first plurality of linear MAC pipelines to the second memory.
20. The integrated circuit of claim 18 wherein:
the first plurality of linear MAC pipelines includes one or more linear MAC pipelines that is/are different from the linear MAC pipelines of the second plurality of linear MAC pipelines.
21. The integrated circuit of claim 18 wherein:
in the second configuration, the first memory is coupled to the second plurality of linear MAC pipelines to store data therefrom, and wherein, in the second configuration, the first memory is configured to only store data.
22. The integrated circuit of claim 18 further including:
a switch interconnect network coupled to the first memory and the plurality of multiplier-accumulator circuits, wherein the switch interconnect network is configurable to couple the inputs of the first plurality of linear MAC pipelines to the first memory in the first configuration.
23. The integrated circuit of claim 18 further including:
a switch interconnect network coupled to the second memory and the plurality of multiplier-accumulator circuits, wherein the switch interconnect network is configurable to couple the outputs of the first plurality of linear MAC pipelines to the second memory in the first configuration.
24. The integrated circuit of claim 18 wherein:
a plurality of multiplier-accumulator circuits of the first plurality of linear MAC pipelines are different from a plurality of multiplier-accumulator circuits of the second plurality of linear MAC pipelines.
25. The integrated circuit of claim 18 wherein:
the first plurality of linear MAC pipelines includes one or more linear MAC pipelines that is/are the same as the linear MAC pipelines of the second plurality of linear MAC pipelines.