Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network

1. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes:

a configurable switch interconnect network, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including:

at least two stages of switch matrices, configured in a hierarchical network, and

a mesh stage of switch matrices, directly connected to the hierarchical network, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage, and

wherein the mesh stage of switch matrices of each logic tile of the plurality of logic tile is directly connected to at least one mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.

2. The integrated circuit of claim 1 wherein the plurality of logic tiles are physically organized in one or more rows and/or one or more columns.

3. The integrated circuit of claim 1 wherein the mesh stage of switch matrices is a highest stage of the plurality of stages of switch matrices.

4. The integrated circuit of claim 1 wherein at least one of the logic tiles is configurable to communicate, during operation of the integrated circuit, with at least one other logic tile via the respective mesh stages.

5. The integrated circuit of claim 1 wherein each switch matrix of the mesh stage of each logic tile is directly connected to only one switch matrix of the switch matrices of the at least two of the stages of switch matrices of the associated configurable switch interconnect network of the logic tile.

6. The integrated circuit of claim 5 wherein the data stored in memory, during operation, controls which input of one or more switches of the plurality of switches is connected to an associated output.

7. The integrated circuit of claim 1 wherein each switch matrix of the mesh stage of switch matrices is electrically coupled between the switch matrices of the first and second stages of the associated configurable switch interconnect network of the logic tile.

8. The integrated circuit of claim 1 wherein:

the mesh stage of switch matrices of each logic tile is a highest stage of the plurality of stages of switch matrices,

at least one of the logic tiles is configurable to communicate, during operation of the integrated circuit, with at least one other logic tile via the respective mesh stages, and

each switch matrix of the mesh stage of each logic tile is directly connected to only one switch matrix of the switch matrices of the at least two of the stages of switch matrices of the associated configurable switch interconnect network of the logic tile.

9. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles, electrically coupled to the control circuitry and the timing circuitry, wherein (i) the logic tiles are physically organized in at least one row and at least one column and (ii) each logic tile is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles, and wherein each logic tile includes:

a configurable switch interconnect network which is electrically coupled to the computing elements, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of stages of switch matrices including:

a first stage of switch matrices configured in a hierarchical network,

a second stage of switch matrices configured in a hierarchical network, and

a third stage of switch matrices, wherein each switch matrix of the third stage includes an output that is directly connected to an input of two or more different switch matrices of the third stage, and wherein the third stage of switch matrices is a highest stage of the plurality of stages of switch matrices; and

wherein the configurable switch interconnect network of each logic tile of the plurality of logic tile is directly connected to the configurable switch interconnect network of at least one other logic tile of the plurality of the logic tiles via the respective third stages of switch matrices.

10. The integrated circuit of claim 9 wherein an output of each switch matrix of the third stage of switch matrices is directly connected to at least one switch in at least three other switch matrices of the third stage of switch matrices of the associated configurable switch interconnect network of the logic tile.

11. The integrated circuit of claim 9 wherein:

each switch matrix of the first stage of switch matrices is configured in a radix-a network, where a is a whole number which is greater than or equal to 3, and

each switch matrix of the second stage of switch matrices is configured in a radix-b, where (i) b is equal to 2 or 3 and (ii) b is not equal to a.

12. The integrated circuit of claim 9 wherein at least one of the logic tiles is configurable to communicate, during operation of the integrated circuit, with at least one other logic tile via the respective third stages.

13. The integrated circuit of claim 9 wherein:

at least one of the logic tiles is configurable to communicate, during operation of the integrated circuit, with at least one other logic tile via the respective third stages, and

each switch matrix of the third stage of each logic tile is directly connected to only one switch matrix of the switch matrices of the first or second stages of switch matrices of the associated configurable switch interconnect network of the logic tile.

14. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles physically organized in at least one row and at least one column and wherein each logic tile (i) is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes:

a configurable switch interconnect network which is electrically coupled to the memory, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of switch matrices and wherein the plurality of switch matrices are arranged in a plurality of stages including:

a first stage of switch matrices configured in a hierarchical network,

a second stage of switch matrices configured in a hierarchical network, and

a third stage of switch matrices, wherein each switch matrix of the third stage includes an output that is directly connected to an input of two or more different switch matrices of the third stage; and

wherein the third stage of switch matrices of the configurable switch interconnect network of each logic tile of the plurality of logic tile is directly connected to the third stage of switch matrices of the configurable switch interconnect network of at least one other logic tile of the plurality of the logic tiles.

15. The integrated circuit of claim 14 wherein the third stage of switch matrices is a highest stage of the plurality of stages of switch matrices of the configurable switch interconnect network of each logic tile of the plurality of logic tile.

16. The integrated circuit of claim 14 wherein:

the plurality of stages of switch matrices includes:

a first stage of switch matrices which is configured in a radix-a network, where a is a whole number which is greater than or equal to 3,

a second stage of switch matrices is configured in a radix-b network, where b is a whole number which is greater than or equal to 3, and

wherein (1) the second stage of switch matrices is located between the first stage of switch matrices and the third stage of switch matrices, and (2) the third stage of switch matrices is a highest stage of the plurality of stages of switch matrices.

17. The integrated circuit of claim 14 wherein each switch matrix of the third stage is directly connected to only one switch matrix of the switch matrices of the first or second stages of switch matrices of the associated configurable switch interconnect network of the logic tile.

18. The integrated circuit of claim 14 wherein the plurality of switch matrices of the configurable switch interconnect network of each logic tile of the plurality of logic tiles further include a fourth stage of switch matrices wherein each switch matrix of the fourth stage includes an output that is directly connected to an input of two or more different switch matrices of the fourth stage of the associated configurable switch interconnect network of the logic tile.

19. The integrated circuit of claim 18 wherein each switch matrix of the fourth stage of switch matrices is electrically coupled between the switch matrices of the first and second stages of the associated configurable switch interconnect network of the logic tile.

20. The integrated circuit of claim 19 wherein the third stage of switch matrices is a highest stage of the plurality of stages of switch matrices of the configurable switch interconnect network of each logic tile of the plurality of logic tiles.