Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same

1. An integrated circuit comprising:

a plurality of computing elements;

a plurality of switches electrically interconnected and arranged in a plurality of switch matrices; and

wherein the plurality of switch matrices are arranged in a plurality of stages including:

a first stage of switch matrices configured in a hierarchical network,

a second stage of switch matrices configured in a hierarchical network, and

a third stage of switch matrices (i) wherein an output of each switch matrix of the third stage of switch matrices is directly connected to an input of at least one switch in each of a plurality of switch matrices of the third stage, and (ii) wherein each switch matrix of the plurality of switch matrices of the third stage is directly connected to only one switch matrix of the switch matrices of the first stage of switch matrices and/or only one of the switch matrix of the second stage of switch matrices.

2. The integrated circuit of claim 1 wherein each switch matrix of the third stage of switch matrices is electrically coupled between the switch matrices of the first and second stages.

3. The integrated circuit of claim 1 wherein each switch matrix of the second stage of switch matrices is electrically coupled between the first and third stages of switch matrices.

4. The integrated circuit of claim 3 wherein:

each switch matrix of the first stage of switch matrices is connected to at least one computing element,

each switch matrix of the second stage of switch matrices is electrically coupled between the switch matrices of the first and third stages.

5. The integrated circuit of claim 4 wherein the third stage of switch matrices is the highest stage of the plurality of stages.

6. The integrated circuit of claim 5 wherein each switch matrix of the first stage of switch matrices is configured in a radix-3 network.

7. The integrated circuit of claim 6 wherein the radix-3 network is a boundary-less radix-3 network.

8. The integrated circuit of claim 5 wherein each switch matrix of the first stage of switch matrices is configured in a radix-4 network.

9. An integrated circuit comprising:

a plurality of computing elements;

a mixed-mode interconnect network, including:

a plurality of switch matrices, wherein (i) each switch matrix of the plurality of switch matrices includes at least one switch and (ii) the plurality of switch matrices are arranged in a plurality of stages including:

a first stage of switch matrices, configured in a hierarchical network, and electrically connected to at least one computing element,

a second stage of switch matrices configured in a hierarchical network and electrically coupled to one or more switches of the switch matrices of the first stage of switch matrices, and

a third stage of switch matrices (i) configured in a mesh network, wherein each switch matrix of the third stage of switch matrices includes a plurality of inputs and a plurality of outputs and wherein each output of a plurality of the outputs of each switch matrix of the third stage of switch matrices is directly connected to an associated input of the plurality of inputs of a plurality of other switch matrices of the third stage and (ii) wherein each switch matrix of the third stage is directly connected to only one switch matrix of the first stage of switch matrices and/or only one switch matrix of the second stage of switch matrices.

10. The integrated circuit of claim 9 wherein:

second stage of switch matrices is located between the first stage of switch matrices and the third stage of switch matrices, and

an output of each switch matrix of the second stage of switch matrices is directly connected to an input of an associated switch matrix of the third stage of switch matrices.

11. The integrated circuit of claim 9 wherein an output of each switch matrix of the third stage of switch matrices is directly connected to at least one switch in at least three other switch matrices of the third stage of switch matrices.

12. The integrated circuit of claim 11 wherein the plurality of stages further includes a fourth stage of switch matrices (i) configured in a mesh network wherein each switch matrix of the fourth stage of switch matrices is directly connected to a switch in each of a plurality of switch matrices of the fourth stage and (ii) electrically coupled to one or more switches of the switch matrices of the first and/or second stages of switch matrices.

13. The integrated circuit of claim 9 wherein third stage of switch matrices is the highest stage of the plurality of stages.

14. The integrated circuit of claim 9 wherein:

each switch matrix of the first stage of switch matrices is configured in a radix-a network, where a is a whole number which is greater than or equal to 3, and

each switch matrix of the second stage of switch matrices is configured in a radix-b, where (i) b is equal to 2 or 3 and (ii) b is not equal to a.

15. The integrated circuit of claim 14 wherein the third stage of switch matrices is the highest stage of the interconnect network.

16. An integrated circuit comprising:

a plurality of computing elements;

a plurality of switch matrices, wherein (i) each switch matrix includes at least one switch and (ii) the plurality of switch matrices are arranged in stages including:

a plurality of stages of switch matrices, configured in a hierarchical network, wherein, each switch matrix of the plurality of stages is connected to a plurality of switch matrices of other stages, and

a first mesh stage of switch matrices which is (i) configured in a mesh network wherein each switch matrix of the first mesh stage of switch matrices is directly connected to at least one switch in each of a plurality of other switch matrices of the first mesh stage and (ii) electrically and directly connected to one or more switches of less than or equal to two of the switch matrices of the plurality of stages of switch matrices.

17. The integrated circuit of claim 16 wherein the first mesh stage of switch matrices is the highest stage.

18. The integrated circuit of claim 17 wherein each switch of the first mesh stage of switch matrices is directly connected to at least one switch in at least three other switch matrices of the first mesh stage.

19. The integrated circuit of claim 16 wherein:

the plurality of stages of switch matrices includes:

a first stage of switch matrices which is configured in a radix-a network, where a is a whole number which is greater than or equal to 3,

a second stage of switch matrices is configured in a radix-b network, where b is a whole number which is greater than or equal to 3, and

a third stage of switch matrices is configured in a radix-c network, where c is equal to 2 or 3, and

wherein (1) the second stage of switch matrices is located between the first stage of switch matrices and the third stage of switch matrices, and (2) the third stage of switch matrices is located between the second stage of switch matrices and the first mesh stage of switch matrices.

20. The integrated circuit of claim 19 wherein the first mesh stage of switch matrices is the highest stage and each switch matrix of the plurality of switch matrices of the first mesh stage is directly connected to only one switch matrix of the plurality of stages of switch matrices.

21. The integrated circuit of claim 16 wherein the plurality of switch matrices, further include a second mesh stage of switch matrices which is (i) configured in a mesh network wherein each switch matrix of the second mesh stage of switch matrices is directly connected to at least one switch in each of a plurality of other switch matrices of the second mesh stage and (ii) electrically coupled to one or more switches of the switch matrices of the plurality of stages of switch matrices.