Clock architecture, including clock mesh fabric for FPGA, and method of operating same

1. An integrated circuit comprising:

an array of logic tiles, wherein the array of logic tiles includes a first plurality of logic tiles and a second plurality of logic tiles, and wherein each logic tile of the array of logic tiles is configurable to electrically connect with at least one other logic tile of the array of logic tiles;

a clock mesh fabric including a clock mesh to provide a mesh clock signal to the first plurality of the logic tiles; and

wherein each logic tile of the first plurality of logic tiles includes:

clock distribution and transmission circuitry, configurable to provide a tile clock to circuitry which performs operations using or based on the tile clock, wherein the clock distribution and transmission circuitry includes:

tile clock generation circuitry configurable to generate a tile clock signal having a skew, wherein the skew of the tile clock signal is balanced with respect to the tile clock signals generated by the tile clock generation circuitry of each logic tile of the first plurality of logic tiles, and

clock selection circuitry, coupled to the clock mesh and the tile clock generation circuitry, configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock of the associated logic tile to the circuitry, of the associated logic tile, which performs operations using or based on the tile clock of the associated logic tile, wherein the tile clock corresponds to the mesh clock signal or the tile clock signal.

2. The integrated circuit of claim 1 wherein:

at least one logic tile of the first plurality of logic tiles receives an external clock signal, wherein the external clock signal is external to the array of logic tiles; and

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry which is configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of each logic tile of the first plurality of logic tiles is coupled in the input clock path of the associated logic tile and is configurable to receive (i) the external clock signal or (ii) a delayed version of the external clock signal from one of the plurality of output clock paths of an adjacent logic tile.

3. The integrated circuit of claim 2 wherein each output clock path of the plurality of output clock paths of each logic tile of the first plurality of logic tiles includes at least one u-turn circuit.

4. The integrated circuit of claim 1 wherein:

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry which is configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of at least one logic tile of the first plurality of logic tiles is coupled in the input clock path of the associated logic tile and is configurable to receive a delayed version of an external clock signal from one of the plurality of output clock paths of an adjacent logic tile, and wherein the external clock signal is external to the array of logic tiles.

5. The integrated circuit of claim 1 wherein the clock selection circuitry of each logic tile of the first plurality of logic tiles includes a clock select multiplexer to receive the mesh clock signal at a first input and the tile clock signal at a second input and responsively output the tile clock at an output of the clock select multiplexer.

6. The integrated circuit of claim 5 wherein the clock select multiplexer further receives one or more input control signals to determine which input of the clock select multiplexer is connected to the output of the clock select multiplexer.

7. The integrated circuit of claim 1 wherein the tile clock generation circuitry of each logic tile of the first plurality of logic tiles includes one or more buffers.

8. The integrated circuit of claim 1 wherein each logic tile of the second plurality of logic tiles includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry which is configurable to transmit a tile output clock signal to one or more logic tiles of the second plurality of logic tiles, and

wherein the tile clock generation circuitry of at least one logic tile of the second plurality of logic tiles is coupled in the input clock path of the associated logic tile and is configurable to receive a delayed version of an external clock signal from one of the plurality of output clock paths of an adjacent logic tile to generate a tile clock signal having a skew, wherein the skew of the tile clock signal is balanced with respect to the tile clock signals generated by the tile clock generation circuitry of at least one other logic tile of the second plurality of logic tiles, and wherein the external clock signal is external to the array of logic tiles.

9. The integrated circuit of claim 8 wherein each output clock path of the plurality of output clock paths of each logic tile of the second plurality of logic tiles includes at least one u-turn circuit.

10. The integrated circuit of claim 9 wherein the at least one of the u-turn circuit of each output clock path of the plurality of output clock paths of each logic tile of the second plurality of logic tiles includes one or more buffers.

11. An integrated circuit comprising:

an array of logic tiles, wherein the array of logic tiles includes a first plurality of logic tiles and a second plurality of logic tiles, and wherein each logic tile of the array of logic tiles is configurable to electrically connect with at least one other logic tile of the array of logic tiles;

a clock mesh fabric including a clock mesh to provide a mesh clock signal to the first plurality of the logic tiles; and

wherein each logic tile of the first plurality of logic tiles includes:

clock distribution and transmission circuitry configurable to provide a tile clock to circuitry which performs operations using or based on the tile clock, wherein the clock distribution and transmission circuitry includes:

tile clock generation circuitry configurable to generate a tile clock signal having a skew, wherein the skew of the tile clock signal is balanced with respect to the tile clock signals generated by the tile clock generation circuitry of each logic tile of the first plurality of logic tiles,

clock selection circuitry, coupled to the clock mesh and the tile clock generation circuitry, configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock of the associated logic tile to the circuitry, of the associated logic tile, which performs operations using or based on the tile clock of the associated logic tile, wherein the tile clock corresponds to the mesh clock signal or the tile clock signal, and

tile clock enable/disable circuitry, coupled to the tile clock generation circuitry, to responsively enable or disable: (i) generation of tile clock signal or (ii) output of the tile clock signal by the tile clock generation circuitry.

12. The integrated circuit of claim 11 wherein the tile clock enable/disable circuitry includes an AND logic gate.

13. The integrated circuit of claim 11 wherein:

at least one logic tile of the first plurality of logic tiles receives an external clock signal, wherein the external clock signal is external to the array of logic tiles; and

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of each logic tile is coupled in the input clock path of the associated logic tile and the tile clock generation circuitry of at least one logic tile of the first plurality of logic tiles is configurable to receive a delayed version of the external clock signal from one of the plurality of output clock paths of an adjacent logic tile.

14. The integrated circuit of claim 11 wherein:

at least one logic tile of the first plurality of logic tiles receives an external clock signal, wherein the external clock signal is external to the array of logic tiles; and

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of each logic tile is coupled in the input clock path of the associated logic tile and the tile clock generation circuitry of at least one logic tile of the first plurality of logic tiles is configurable to (i) receive a delayed version of the external clock signal from one of the plurality of output clock paths of an adjacent logic tile and (ii) generate a tile clock for the associated at least one logic tile.

15. The integrated circuit of claim 14 wherein each output clock path of the plurality of output clock paths of each logic tile of the first plurality of logic tiles includes at least one u-turn circuit.

16. The integrated circuit of claim 11 wherein the clock selection circuitry of each logic tile of the first plurality of logic tiles includes a clock select multiplexer which (i) is configurable of receive the mesh clock signal at a first input and the tile clock signal at a second input and (ii) responsively outputs the tile clock at an output of the clock select multiplexer.

17. An integrated circuit comprising:

an array of logic tiles, wherein the array of logic tiles includes a first plurality of logic tiles and a second plurality of logic tiles, and wherein each logic tile of the array of logic tiles is configurable to electrically connect with at least one other logic tile of the array of logic tiles;

a clock mesh fabric including a clock mesh to provide a mesh clock signal to the first plurality of the logic tiles; and

wherein each logic tile of the first plurality of logic tiles includes:

clock distribution and transmission circuitry configurable to provide a tile clock to circuitry which performs operations using or based on the tile clock, wherein the clock distribution and transmission circuitry includes:

tile clock generation circuitry configurable to generate a tile clock signal having a skew, wherein the skew of the tile clock signal is balanced with respect to the tile clock signals generated by the tile clock generation circuitry of each logic tile of the first plurality of logic tiles,

clock selection circuitry, coupled to the clock mesh and the tile clock generation circuitry, configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock of the associated logic tile to the circuitry, of the associated logic tile, which performs operations using or based on the tile clock of the associated logic tile, wherein the tile clock corresponds to the mesh clock signal or the tile clock signal, the clock selection circuitry including:

a clock select multiplexer which (i) is configurable to receive the mesh clock signal at a first input and the tile clock signal at a second input and (ii) responsively outputs the tile clock at an output of the clock select multiplexer, and

tile clock enable/disable circuitry, coupled to the tile clock generation circuitry and the clock select multiplexer, to responsively disable the tile clock signal applied to the second input of the clock select multiplexer.

18. The integrated circuit of claim 17 wherein the tile clock enable/disable circuitry includes an AND logic gate.

19. The integrated circuit of claim 17 wherein:

at least one logic tile of the first plurality of logic tiles receives an external clock signal, wherein the external clock signal is external to the array of logic tiles; and

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of each logic tile is coupled in the input clock path of the associated logic tile and is configurable to receive (i) the external clock signal or (ii) a delayed version of the external clock signal from one of the plurality of output clock paths of an adjacent logic tile.

20. The integrated circuit of claim 19 wherein each output clock path of the plurality of output clock paths of each logic tile of the first plurality of logic tiles includes at least one u-turn circuit.

21. The integrated circuit of claim 17 wherein:

at least one logic tile of the first plurality of logic tiles receives an external clock signal, wherein the external clock signal is external to the array of logic tiles; and

each logic tile of the first plurality of logic tiles further includes:

at least one input clock path, wherein the input clock path includes circuitry configurable to receive an input clock signal, and

a plurality of output clock paths, wherein each output clock path includes circuitry configurable to transmit a tile output clock signal to one or more logic tiles of the first plurality of logic tiles; and

wherein the tile clock generation circuitry of each logic tile is coupled in the input clock path of the associated logic tile and the tile clock generation circuitry of at least one logic tile of the first plurality of logic tiles is configurable to (i) receive a delayed version of the external clock signal from one of the plurality of output clock paths of an adjacent logic tile and (ii) generate a tile clock for the associated at least one logic tile.