FPGA implementing partial datapath processing, and method of operating same
An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.
1. An integrated circuit comprising:
an FPGA including:
an input to receive an input data stream wherein the input data stream includes a first portion and a second portion;
logic circuitry to generate a processed data stream by processing only the first portion of the input data stream via first data processing operation;
an output to output the processed data stream;
an ASIC, having a fixed data processing path, including:
an input to receive the input data stream, wherein the input is coupled to the fixed data processing path;
data alignment circuitry, coupled to the input of the ASIC, to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the logic circuitry of the FPGA; and
data combining circuitry, coupled to the output of the FPGA and the data alignment circuitry, to generate output data using the processed data stream and the second portion of the input data stream from the data alignment circuitry.
2. The integrated circuit of claim 1 wherein the data alignment circuitry includes:
masking control circuitry to delete the first portion of the input data stream from the input data stream received by the input of the logic circuitry.
3. The integrated circuit of claim 1 wherein the data alignment circuitry further includes:
circuitry to temporally synchronize the second portion of the input data stream with a processing time of the first portion of the input data stream by the FPGA.
4. The integrated circuit of claim 1 wherein the data alignment circuitry further includes FIFO circuitry.
5. The integrated circuit of claim 1 wherein the data combining circuitry includes circuitry to generate the output data by interleaving or concatenating (i) data of the processed data stream and (ii) data of the second portion of the input data stream.
6. The integrated circuit of claim 1 wherein the data combining circuitry includes a logic OR circuitry to generate the output data using the processed data stream and the second portion of the input data stream from the data alignment circuitry.
7. The integrated circuit of claim 1 wherein the data combining circuitry includes a concatenation circuitry to generate the output data using the processed data stream and the second portion of the input data stream from the data alignment circuitry.
8. The integrated circuit of claim 1 wherein the first data processing operation includes digital signal processing, encoding, decoding, encrypting, and/or decrypting.
9. An integrated circuit comprising:
an embedded FPGA including:
an input to receive an input data stream wherein the input data stream includes a first portion and a second portion;
processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation;
an output to output the processed data;
logic circuitry, separate from the embedded FPGA, including:
an input to receive the input data stream;
data alignment circuitry, coupled to the input of the logic circuitry, to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry of the embedded FPGA; and
data combining circuitry, coupled to the output of the embedded FPGA and the data alignment circuitry, to generate an output data stream using the processed data and the second portion of the input data stream received from the data alignment circuitry.
10. The integrated circuit of claim 9 wherein the data alignment circuitry includes:
masking control circuitry to delete the data of the first portion of the input data stream from the input data stream received by the input of the logic circuitry.
11. The integrated circuit of claim 9 wherein the data alignment circuitry further includes:
circuitry to temporally synchronize the second portion of the input data stream with a processing time of the first portion of the input data stream by the processing circuitry of the embedded FPGA.
12. The integrated circuit of claim 9 wherein the data alignment circuitry further includes FIFO circuitry.
13. The integrated circuit of claim 9 wherein the data combining circuitry includes circuitry to generate the output data stream by interleaving data of the processed data and data of the second portion of the input data stream.
14. The integrated circuit of claim 9 wherein the data combining circuitry includes circuitry to generate the output data stream by concatenating data of the processed data and data of the second portion of the input data stream.
15. The integrated circuit of claim 9 wherein the data combining circuitry includes a logic OR circuitry to generate the output data stream using the processed data and the second portion of the input data stream from the data alignment circuitry.
16. The integrated circuit of claim 9 wherein the data combining circuitry includes a concatenation circuitry to generate output data stream using the processed data and the second portion of the input data stream from the data alignment circuitry.
17. The integrated circuit of claim 9 wherein the data processing operation includes digital signal processing, encoding, decoding, encrypting, and/or decrypting.
18. An integrated circuit comprising:
an embedded FPGA including:
an input to receive an input data stream wherein the input data stream includes a first portion and a second portion;
processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation;
an output to output the processed data;
logic circuitry, separate from the embedded FPGA, including:
an input to receive the input data stream;
data alignment circuitry, coupled to the input of the logic circuitry, of the logic circuitry, the data alignment circuitry includes:
circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry of the embedded FPGA, and
masking control circuitry to delete the data of the first portion of the input data stream from the input data stream received by the input of the logic circuitry; and
data combining circuitry, coupled to the output of the embedded FPGA and the data alignment circuitry, to generate an output data stream using the processed data and the second portion of the input data stream received from the data alignment circuitry.
19. The integrated circuit of claim 18 wherein the data processing operation includes digital signal processing, encoding, decoding, encrypting, and/or decrypting.
20. The integrated circuit of claim 18 wherein the data combining circuitry includes circuitry to generate the output data stream by interleaving or concatenating (i) data of the processed data and (ii) data of the second portion of the input data stream.