IP Library › Granted Patent US 11,277,135

Granted Patent B2

US 11,277,135 · App. 17/106,124 · Granted Mar 15, 2022

Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA

Inventors: Yongning Liu (San Ramon, CA); Fan Mo (San Jose, CA); Cheng C. Wang (San Jose, CA)

Assignee: Flex Logix Technologies, Inc.

H03K19/17744 H03K19/17732 H03K19/17796

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Quick Facts

Patent No.: US 11,277,135
App. No.: 17/106,124
Granted: Mar 15, 2022
Kind: B2

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Abstract

A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.

Claims (66)

1. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a first plurality of logic tiles and a second plurality of logic tiles, wherein each logic tile of the first plurality of logic tiles and a second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points, to interconnect logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:

routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles wherein the start/end point of each tile-to-tile interconnect in the first plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the first plurality of tile-to-tile interconnects;

after routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles wherein the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the second plurality of tile-to-tile interconnects;

wherein routing the second plurality of tile-to-tile interconnects in the second plurality of logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect of the second plurality of tile-to-tile interconnects that was routed in the second plurality of logic tiles to at least one start/end point of a tile-to-tile interconnect of the first plurality of tile-to-tile interconnects that was routed in the first plurality of logic tiles; and

detecting a conflict of at least one routing interconnect path and, in response, re-routing at least one tile-to-tile interconnect of the first plurality of tile-to-tile interconnects or at least one tile-to-tile interconnect of the second plurality of tile-to-tile interconnects.

2. The method of claim 1 further including:

routing the first plurality of tile-to-tile interconnects in the first plurality of logic tiles temporally in parallel.

3. The method of claim 1 further including:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles.

4. The method of claim 3 wherein:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles includes programming switches of the logic tile interconnect network of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles.

5. The method of claim 4 wherein:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles further includes programming switches of the logic tile interconnect network of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles to connect to one or more inputs/outputs of a computing element.

6. The method of claim 1 further including:

routing the first plurality of tile-to-tile interconnects in the first plurality of logic tiles temporally in parallel, and

after routing the first plurality of tile-to-tile interconnects in the first plurality of logic tiles temporally in parallel, routing the second plurality of tile-to-tile interconnects in the second plurality of logic tiles temporally in parallel.

7. The method of claim 1 wherein:

re-routing at least one tile-to-tile interconnect of the first plurality of tile-to-tile interconnects or at least one tile-to-tile interconnect of the second plurality of tile-to-tile interconnects further includes re-routing at least one tile-to-tile interconnect of the first plurality of tile-to-tile interconnects and at least one tile-to-tile interconnect of the second plurality of tile-to-tile interconnects.

8. The method of claim 7 wherein:

the at least one tile-to-tile interconnect of the first plurality of tile-to-tile interconnects and the at least one tile-to-tile interconnect of the second plurality of tile-to-tile interconnects are associated tile-to-tile interconnects.

9. The method of claim 1 wherein:

each logic tile of the first plurality of logic tiles is non-contiguous relative to all other logic tiles of the first plurality of logic tiles, and

each logic tile of the second plurality of logic tiles is non-contiguous relative to all other logic tiles of the second plurality of logic tiles.

10. The method of claim 1 wherein:

routing the first tile-to-tile interconnects and routing the second plurality of tile-to-tile interconnects include routing the first and second plurality of tile-to-tile interconnects into a mesh network.

11. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a first plurality of non-contiguous logic tiles, wherein each logic tile of the first plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a second plurality of non-contiguous logic tiles, wherein each logic tile of the second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, and (iii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points to interconnect the logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:

routing a first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles temporally in parallel, wherein the start/end point of each tile-to-tile interconnect of the first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the first plurality of tile-to-tile interconnects;

after routing the first plurality of tile-to-tile interconnects in a first plurality of non-contiguous logic tiles, routing a second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles temporally in parallel, wherein the start/end point of each tile-to-tile interconnect of the first plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the second plurality of tile-to-tile interconnects;

wherein routing the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect of the second plurality of tile-to-tile interconnects that was routed in the second plurality of logic tiles to at least one start/end point of a tile-to-tile interconnect of the first plurality of tile-to-tile interconnects that was routed in the first plurality of non-contiguous logic tiles; and

12. The method of claim 11 wherein:

each logic tile of the first plurality of non-contiguous logic tiles is contiguous to at least one logic tile of the second plurality of non-contiguous logic tiles.

13. The method of claim 11 further including:

routing the logic tile interconnects of each logic tile of the first plurality of non-contiguous logic tiles, and

routing the logic tile interconnects of each logic tile of the second plurality of non-contiguous logic tiles.

14. The method of claim 11 further including:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles by programming switches of the logic tile interconnect network of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles, wherein:

routing the logic tile interconnects of each logic tile of the first plurality of non-contiguous logic tiles and second plurality of non-contiguous logic tiles includes routing logic tile interconnects of a plurality of stages including at least one hierarchical stage and at least one mesh stage, and

routing the first tile-to-tile interconnects and second plurality of tile-to-tile interconnects include routing the first and second plurality of tile-to-tile interconnects into a mesh network.

15. The method of claim 11 wherein:

routing the first plurality of tile-to-tile interconnects of each logic tile of the first plurality of non-contiguous logic tiles includes programming three or more switches of the logic tile interconnect network of each logic tile of the first plurality of logic tiles that are connected to at least one of the first plurality of tile-to-tile interconnects, and

routing the second plurality of tile-to-tile interconnects of each logic tile of the second plurality of non-contiguous logic tiles includes programming three or more switches of the logic tile interconnect network of each logic tile of the second plurality of logic tiles that are connected to at least one of the second plurality of tile-to-tile interconnects.

16. The method of claim 15 further including:

routing the logic tile interconnects of each logic tile of the first and second plurality of non-contiguous logic tiles and wherein:

17. The method of claim 16 wherein:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and the second plurality of logic tiles further includes programming switches of the logic tile interconnect network of each logic tile of the first and second plurality of non-contiguous logic tiles to connect to one or more inputs/outputs of a computing element.

18. The method of claim 11 wherein:

19. The method of claim 18 wherein:

20. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a first plurality of non-contiguous logic tiles, wherein each logic tile of the first plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a second plurality of non-contiguous logic tiles, wherein each logic tile of the second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, and (iii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points to interconnect the logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:

routing a first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles, wherein the start/end point of each tile-to-tile interconnect in the first plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the first plurality of tile-to-tile interconnects, wherein a portion of the first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles are routed sequentially;

after routing the first plurality of tile-to-tile interconnects in a first plurality of non-contiguous logic tiles, routing a second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles, wherein the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects of the second plurality of tile-to-tile interconnects, wherein a portion of the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles are routed sequentially;

wherein routing the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect of the second plurality of tile-to-tile interconnects to at least one start/end point of a tile-to-tile interconnect of the first plurality of tile-to-tile interconnects that was routed in the first plurality of non-contiguous logic tiles; and

21. The method of claim 20 wherein:

each logic tile of the first plurality of non-contiguous logic tiles is contiguous to at least one logic tile of the second plurality of non-contiguous logic tiles.

22. The method of claim 20 further including:

routing the logic tile interconnects of each logic tile of the first plurality of logic tiles and second plurality of logic tiles by programming switches of the logic tile interconnect network of each logic tile of the first plurality of logic tiles and second plurality of logic tiles, wherein:

routing the first plurality of tile-to-tile interconnects and the second plurality of tile-to-tile interconnects include routing the first and second plurality of tile-to-tile interconnects into a mesh network.

23. The method of claim 20 wherein:

24. The method of claim 23 wherein:

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2024

From: FLEX LOGIX TECHNOLOGIES, INC.

To: ANALOG DEVICES, INC.

Reel/Frame 069409/0035 →

Continuity (3)

Division 16579766 · Sep 23, 2019

Provisional Application 62735988 · Sep 25, 2018

Related Publication 20210083674A1 · Mar 18, 2021