Multiply-Accumulate Engine with Non-Normalized Floating-Point Accumulator

1 . A floating-point summation circuit implemented within an integrated circuit device, the floating-point summation circuit comprising:

inputs to receive:

a first normalized floating-point operand having an exponent field and a fraction field, and

a non-normalized floating-point operand having an exponent field and a fraction field, the fraction field of the non-normalized floating-point operand having a first significant bit in any of at least two different bit positions;

normalizing circuitry to generate, at least by normalizing the fraction field of the non-normalized floating-point operand, a second normalized floating-point operand having a value corresponding to that of the non-normalized floating point operand; and

adder circuitry to generate a floating-point sum by adding the first and second normalized floating-point operands.

2 . The floating-point summation circuit of claim 1 wherein the adder circuitry to generate the floating-point sum by adding the first and second normalized floating-point operands comprises circuitry to generate the floating-point sum in a normalized format.

3 . The floating-point summation circuit of claim 2 further comprising circuitry to convert the floating-point sum from the normalized format to a non-normalized format, the non-normalized format consistent with a format of the non-normalized floating-point operand.

4 . The floating-point summation circuit of claim 3 wherein:

the inputs to receive the first normalized floating-point operand and the non-normalized floating-point operand comprises a first input to receive the non-normalized floating-point operand from an operand register during a first clock cycle; and

the circuitry to convert the floating-point sum from the normalized format to a non-normalized format outputs the floating-point sum to the operand register in the non-normalized format to enable the floating-point sum in the non-normalized format to be loaded into the operand register following conclusion of the first clock cycle.

5 . The floating-point summation circuit of claim 4 wherein the inputs to receive the first normalized floating-point operand and the non-normalized floating-point operand comprises a second input to receive the first normalized floating-point operand during the first clock cycle, and wherein the inputs enable reception, during a second clock cycle that transpires after the first clock cycle, of a third normalized floating-point operand and, as an updated non-normalized floating-point operand, the floating-point sum in the non-normalized format.

6 . The floating-point summation circuit of claim 1 wherein the normalizing circuitry to generate the second normalized floating-point operand comprises circuitry to normalize the non-normalized floating-point operand based on bit values within an overflow region of the fraction field of the non-normalized floating-point operand.

7 . The floating-point summation circuit of claim 1 wherein the exponent field of the first normalized floating-point operand is larger than the exponent field of the non-normalized floating-point operand.

8 . The floating-point summation circuit of claim 1 wherein the fraction field of the first normalized floating-point operand includes a sign bit and a magnitude field that collectively implement a sign-magnitude numeric format, and wherein the fraction field of the non-normalized floating-point operand is encoded in a two'-complement numeric format.

9 . The floating-point summation circuit of claim 1 wherein the normalizing circuitry to generate the second normalized floating-point operand comprises circuitry to generate both an incremented instance and a decremented instance of the exponent field of the non-normalized floating-point operand and to select either the incremented instance or the decremented instance to be output as a selected exponent field.

10 . The floating-point summation circuit of claim 1 wherein the normalizing circuitry to generate the second normalized floating-point operand comprises circuitry to generate both a right-shifted instance and a left-shifted instance of the fraction field of the non-normalized floating-point operand and to select either the right-shifted instance or the left-shifted instance to be output as a selected fraction field.

11 . A method of operation within a floating-point summation circuit implemented within an integrated circuit device, the method comprising:

receiving a first normalized floating-point operand having an exponent field and a fraction field;

receiving a non-normalized floating-point operand having an exponent field and a fraction field, the fraction field of the non-normalized floating-point operand having a first significant bit in any of at least two different bit positions;

generating, at least by normalizing the fraction field of the non-normalized floating-point operand, a second normalized floating-point operand having a value corresponding to that of the non-normalized floating point operand; and

adding the first and second normalized floating-point operands to produce a floating-point sum.

12 . The method of claim 11 wherein adding the first and second normalized floating-point operands comprises to produce the floating-point sum comprises generating the floating-point sum in a normalized format.

13 . The method of claim 12 further comprising converting the floating-point sum from the normalized format to a non-normalized format, the non-normalized format consistent with a format of the non-normalized floating-point operand.

14 . The method of claim 13 wherein (i) receiving the first normalized floating-point operand comprises receiving the first normalized floating-point operand during a first clock cycle and (ii) receiving the non-normalized floating-point operand comprises receiving the non-normalized floating-point operand from an operand register during the first clock cycle, the method further comprising loading the floating-point sum in the non-normalized format into the operand register following conclusion of the first clock cycle.

15 . The method of claim 14 further comprising receiving the first normalized floating-point operand comprises receiving the first normalized floating-point operand during the first clock cycle, the method further comprising receiving, during a second clock cycle that transpires after the first clock cycle, a third normalized floating-point operand and, as an updated non-normalized floating-point operand, the floating-point sum in the non-normalized format.

16 . The method of claim 11 wherein generating the second normalized floating-point operand comprises normalizing the non-normalized floating-point operand based on bit values within an overflow region of the fraction field of the non-normalized floating-point operand.

17 . The method of claim 11 wherein the exponent field of the first normalized floating-point operand is larger than the exponent field of the non-normalized floating-point operand.

18 . The method of claim 11 wherein the fraction field of the first normalized floating-point operand includes a sign bit and a magnitude field that collectively implement a sign-magnitude numeric format, and wherein the fraction field of the non-normalized floating-point operand is encoded in a two's-complement numeric format.

19 . The method of claim 11 wherein generating the second normalized floating-point operand comprises generating both an incremented instance and a decremented instance of the exponent field of the non-normalized floating-point operand and selecting either the incremented instance or the decremented instance to be output as a selected exponent field.

20 . The method of claim 11 wherein generating the second normalized floating-point operand comprises generating both a right-shifted instance and a left-shifted instance of the fraction field of the non-normalized floating-point operand selecting either the right-shifted instance or the left-shifted instance to be output as a selected fraction field.

21 . A floating-point summation circuit implemented within an integrated circuit device, the floating-point summation circuit comprising:

means for receiving:

a first normalized floating-point operand having an exponent field and a fraction field, and

a non-normalized floating-point operand having an exponent field and a fraction field, the fraction field of the non-normalized floating-point operand having a first significant bit in any of at least two different bit positions;

means for generating, at least by normalizing the fraction field of the non-normalized floating-point operand, a second normalized floating-point operand having a value corresponding to that of the non-normalized floating point operand; and

means for generating a floating-point sum by adding the first and second normalized floating-point operands.