IP Library › Granted Patent US 10,680,616

Granted Patent B2

US 10,680,616 · App. 15/978,235 · Granted Jun 9, 2020

Block memory layout and architecture for programmable logic IC, and method of operating same

Inventors: Geoffrey R. Tate (Portola Valley, CA); Cheng C. Wang (San Jose, CA)

Assignee: Flex Logix Technologies, Inc.

H03K19/1776 H03K19/1737 H03K19/17728 H03K19/17736 H03K19/17744 G11C5/025

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Quick Facts

Patent No.: US 10,680,616
App. No.: 15/978,235
Granted: Jun 9, 2020
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An integrated circuit comprising a first memory array and programmable/configurable logic circuitry including a plurality of logic tiles wherein each logic tile includes a perimeter, a plurality of external I/O disposed in an I/O layout on the perimeter, wherein the I/O layout of each tile is identical. Each external I/O is configurable as an external I/O to connect to and communicate with external circuitry, or a memory I/O to point-to-point connect to memory located adjacent thereto, or an unused I/O. The first memory array is physically adjacent to a first logic tile on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry, and point-to-point connected to the memory I/O. In operation, circuitry of the first logic tile is configured to read data from and write data to the first memory array via the memory I/O.

Claims (85)

1. An integrated circuit comprising:

programmable/configurable logic circuitry having a periphery, the programmable/configurable logic circuitry includes:

a first memory array; and

a plurality of logic tiles organized in an array, wherein each logic tile of the plurality of logic tiles includes:

an interconnect network including a plurality of multiplexers,

a plurality of interconnect I/O to connect to the interconnect network and one or more interconnect I/O of one or more other logic tiles of the plurality of logic tiles,

a perimeter,

a plurality of I/O disposed in an I/O layout on the perimeter of the logic tile, wherein:

the I/O layout of each logic tile is identical,

each I/O of the I/O layout is configurable as (i) an external I/O to connect to and communicate with circuitry external to the programmable/configurable logic circuitry, or (ii) a memory I/O to point-to-point connect to memory physically located adjacent thereto, or (iii) an unused I/O, and

circuitry configurable to read data from and write data to memory via associated memory I/O;

wherein:

the first memory array is (i) located between and adjacent to first and second logic tiles of the plurality of logic tiles on a first portion of the perimeter of each of the first and second logic tiles which is interior to the periphery of the programmable/configurable logic circuitry and (ii) point-to-point connected to the memory I/O located on the first portion of the perimeter of the first logic tile which is adjacent to the first memory array wherein the first memory array is directly connected to the memory I/O located on the first portion of the perimeter of the first logic tile,

a second portion of the perimeter of the first logic tile forms at least a portion of the periphery of the programmable/configurable logic circuitry, and

external I/O is disposed on the second portion of the perimeter of the first logic tile and is configured to connect to and communicate with circuitry external to the programmable/configurable logic circuitry; and

in operation of the programmable/configurable logic circuitry, the circuitry of the first logic tile is configured to:

apply address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the first logic tile, to read data from the first memory array, and

apply data, address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the first logic tile, to write data to the first memory array.

2. The integrated circuit of claim 1 wherein:

the first memory array is point-to-point connected to the memory I/O located on the first portion of the perimeter of the second logic tile which is adjacent to the first memory array, wherein the first memory array is directly connected to the memory I/O located on the first portion of the perimeter of the second logic tile; and

in operation of the programmable/configurable logic circuitry, the circuitry of the second logic tile is configured to:

apply address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the second logic tile, to read data from the first memory array into the second logic tile via the memory I/O located on the first portion of the perimeter of the second logic tile, and

apply data, address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the second logic tile, to write data to the first memory array.

3. The integrated circuit of claim 1 wherein the first memory array is SRAM, DRAM or MRAM.

4. The integrated circuit of claim 3 wherein the first memory array includes parity or ECC circuitry.

5. The integrated circuit of claim 3 wherein the first memory array is a dual port memory.

6. The integrated circuit of claim 1 wherein the plurality of logic tiles are configured in an array having a plurality of rows and a plurality of columns of logic tiles.

7. An integrated circuit comprising:

programmable/configurable logic circuitry having a periphery, the programmable/configurable logic circuitry includes:

a first memory array; and

a plurality of logic tiles, wherein each logic tile of the plurality of logic tiles includes:

an interconnect network including a plurality of multiplexers,

a plurality of interconnect I/O to connect to the interconnect network and one or more interconnect I/O of one or more other logic tiles of the plurality of logic tiles,

a perimeter,

a plurality of I/O disposed in an I/O layout on the perimeter of the logic tile, wherein:

the I/O layout of each logic tile is identical,

circuitry configurable to read data from and write data to memory via associated memory I/O;

wherein:

the first memory array is (i) physically adjacent to a first logic tile of the plurality of logic tiles on a first portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry and (ii) point-to-point connected to the memory I/O located on the first portion of the perimeter of the first logic tile which is adjacent to the first memory array wherein the first memory array is directly connected to the memory I/O located on the first portion of the perimeter of the first logic tile which is adjacent to the first memory array,

a second portion of the perimeter of the first logic tile forms a first portion of the periphery of the programmable/configurable logic circuitry, and

in operation of the programmable/configurable logic circuitry, the circuitry of the first logic tile is configured to:

apply address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the first logic tile, to read data from the first memory array into the first logic tile via the memory I/O located on the first portion of the perimeter of the first logic tile, and

apply data, address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the first logic tile, to write data to the first memory array.

8. The integrated circuit of claim 7 wherein:

a third portion of the perimeter of the first logic tile forms a second portion of the periphery of the programmable/configurable logic circuitry, and

external I/O is disposed on the third portion of the perimeter of the first logic tile and is configured to connect to and communicate with circuitry external to the programmable/configurable logic circuitry.

9. The integrated circuit of claim 7 wherein:

programmable/configurable logic circuitry further includes a second memory array,

the second memory array is (i) physically adjacent to the first logic tile of the plurality of logic tiles on a second portion of the perimeter of the first logic tile which is interior to the periphery of the programmable/configurable logic circuitry and (ii) point-to-point connected to the memory I/O located on the second portion of the perimeter of the first logic tile which is adjacent to the second memory array wherein the second memory array is directly connected to the memory I/O located on the second portion of the perimeter of the first logic tile which is adjacent to the second memory array, and

in operation of the programmable/configurable logic circuitry, the circuitry of the first logic tile is configured to:

apply address and control signals to the second memory array, via the memory I/O located on the second portion of the perimeter of the first logic tile, to read data from the second memory array, and

apply data, address and control signals to the second memory array, via the memory I/O located on the second portion of the perimeter of the first logic tile, to write data to the second memory array.

10. The integrated circuit of claim 9 wherein:

a third portion of the perimeter of the first logic tile forms a first portion of the periphery of the programmable/configurable logic circuitry, and

11. The integrated circuit of claim 7 wherein the first memory array is SRAM, DRAM or MRAM.

12. The integrated circuit of claim 11 wherein the first memory array includes parity or ECC circuitry.

13. The integrated circuit of claim 11 wherein the first memory array is a dual port memory.

14. An integrated circuit comprising:

programmable/configurable logic circuitry having a periphery, the programmable/configurable logic circuitry includes:

a first memory array; and

a plurality of logic tiles, wherein each logic tile of the plurality of logic tiles includes:

an interconnect network including a plurality of multiplexers,

a plurality of interconnect I/O to connect to the interconnect network and one or more interconnect I/O of one or more other logic tiles of the plurality of logic tiles,

a perimeter,

a plurality of I/O disposed in an I/O layout on the perimeter of the logic tile, wherein:

the I/O layout of each logic tile is identical,

circuitry configurable to read data from and write data to memory via associated memory I/O;

wherein:

the programmable/configurable logic circuitry further includes a second memory array, wherein:

a third portion of the perimeter of the first logic tile forms a first portion of the periphery of the programmable/configurable logic circuitry, and

in operation of the programmable/configurable logic circuitry, the circuitry of the first logic tile is configured to:

apply data, address and control signals to the first memory array, via the memory I/O located on the first portion of the perimeter of the first logic tile, to write data to the first memory array, and

apply address and control signals to the second memory array, via the memory I/O located on the second portion of the perimeter of the first logic tile, to read data from the second memory array, and

15. The integrated circuit of claim 14 wherein the first memory array is SRAM, DRAM or MRAM.

16. The integrated circuit of claim 15 wherein the first memory array includes parity or ECC circuitry.

17. The integrated circuit of claim 15 wherein the first memory array is a dual port memory.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2024

From: FLEX LOGIX TECHNOLOGIES, INC.

To: ANALOG DEVICES, INC.

Reel/Frame 069409/0035 →

Continuity (3)

Division 15239958 · Aug 18, 2016

Provisional Application 62213080 · Sep 1, 2015

Related Publication 20180262198A1 · Sep 13, 2018