Test circuitry and techniques for logic tiles of FPGA

1. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one other logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes:

a normal operating mode,

a test mode,

an interconnect network including a plurality of multiplexers, wherein during operation of the field programmable gate array, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one other adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode, and

a plurality of bitcells to store data, wherein each bitcell includes a write enable control and at least one data input; and

control circuitry, electrically connected to each logic tile of the plurality of logic tiles, to enable concurrently writing configuration test data into the plurality of bitcells of each logic tile of the plurality of logic tiles in response to a test mode control signal of a test sequence wherein the configuration test data is written into the plurality of the bitcells of each logic tile of the plurality of logic tiles concurrently, during the test sequence, by enabling the write enable control of the plurality of the bitcells of each logic tile of the plurality of logic tiles and concurrently providing configuration test data to the at least one data input of each bit cell of the plurality of the bitcells of each logic tile of the plurality of logic tiles.

2. The integrated circuit of claim 1 further including:

test mode control circuitry, electrically connected to each logic tile of the plurality of logic tiles and configurable to issue the test mode control signal.

3. The integrated circuit of claim 1 further including:

test mode control circuitry, electrically connected to each logic tile of the plurality of logic tiles and configurable to issue a control signal wherein, in response, circuitry of each logic tile of the plurality of logic tiles undergoes the test sequence concurrently.

4. The integrated circuit of claim 1 wherein:

isolation circuitry, connected between the interconnect network of the associated logic tile and the interconnect network of each adjacent logic tile, configurable to electrically disconnect the interconnect network of each logic tile of the plurality of logic tiles from the interconnect network of each logic tile of the other logic tiles of the plurality of logic tiles.

5. The integrated circuit of claim 1 wherein:

the isolation circuitry includes one or more multiplexers, wherein each multiplexer of the isolation circuitry includes: (i) a first input connected to a tile-to-tile interconnect providing an input from the interconnect network of another logic tile of the plurality of logic tiles and (ii) a second input connected to a tile-to-tile interconnect providing an output from the interconnect network of the associated logic tile.

6. The integrated circuit of claim 5 further including:

test mode control circuitry, electrically connected to each logic tile of the plurality of logic tiles and configurable to concurrently issuing one or more control signals to the first isolation circuitry of each of the logic tiles of the plurality of logic tiles wherein, in response, each logic tile of the plurality of logic tiles is in the test mode.

7. The integrated circuit of claim 1 wherein:

the isolation circuitry includes one or more multiplexers, wherein each multiplexer of the isolation circuitry includes: (i) a first input connected to a tile-to-tile interconnect providing an input from the interconnect network of another logic tile of the plurality of logic tiles, (ii) a second input connected to a tile-to-tile interconnect providing an output from the interconnect network of the associated logic tile and (iii) an output connected to an input of a stage of the interconnect network of the associated logic tile.

8. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one other logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes:

a normal operating mode,

a test mode,

an interconnect network including a plurality of multiplexers, wherein during operation of the field programmable gate array, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one other adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode, and

a plurality of reconfigurable building block I/O logic, wherein each reconfiqurable building block I/O logic includes at least one data input; and

control circuitry, electrically connected to each logic tile of the plurality of logic tiles, to enable concurrently writing configuration test data into the plurality of reconfiqurable building block I/O logic of each logic tile of the plurality of logic tiles in response to a test mode control signal of a test sequence wherein the configuration test data is written into the plurality of reconfigurable building block I/O logic of each logic tile of the plurality of logic tiles concurrently, during the test sequence, by concurrently providing configuration test data to the at least one data input of the plurality of the reconfiqurable building block I/O logic of each logic tile of the plurality of logic tiles.

9. The integrated circuit of claim 8 further including:

isolation circuitry, located at an input to each of the plurality of reconfigurable building block I/O logic of the logic tile, configurable to responsively disconnect the input to the reconfigurable building block I/O logic of the logic tile from circuitry external to the logic tile in the test mode to thereby electrically disconnect the plurality of reconfigurable building block I/O logic from circuitry external to the logic tile in the test mode.

10. The integrated circuit of claim 9 wherein:

the isolation circuitry includes one or more multiplexers, wherein each multiplexer of the isolation circuitry includes: (i) a first input connected to circuitry external to associated logic tile and (ii) a second input connected to an output from the associated reconfigurable building block I/O logic of the associated logic tile.

11. The integrated circuit of claim 10 wherein:

each multiplexer of the second isolation circuitry, in the test mode, is capable of connecting an output from the associated reconfigurable building block I/O logic of the associated logic tile to its output.

12. The integrated circuit of claim 11 further including:

test mode control circuitry, configurable to concurrently issue one or more control signals to the isolation circuitry of each of the logic tiles of the plurality of logic tiles wherein, in response, each logic tile is in the test mode.

13. A method of testing an integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein each logic tile includes (a) a plurality of bitcells, each bitcell having a write enable control and at least one data input, (b) a plurality of reconfigurable building block I/O logic, each reconfiqurable building block I/O logic having at least one data input, and (c) an interconnect network having a plurality of multiplexers, wherein during a normal operating mode of the field programmable gate array, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one other logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects, the method comprising:

providing a test mode command to each logic tile of the plurality of logic tiles to configure each logic tile of the plurality of logic tiles for test, wherein in response, the field programmable gate array is in a test mode;

concurrently writing first configuration test data into the plurality of bitcells of each logic tile of the plurality of logic tiles, when the field programmable gate array is in the test mode, by:

enabling the write enable control of the plurality of the bitcells of each logic tile of the plurality of logic tiles and concurrently providing first configuration test data to the at least one data input of each bitcell of the plurality of the bitcells of each logic tile of the plurality of logic tiles;

after concurrently writing first configuration test data into the plurality of bitcells of each logic tile of the plurality of logic tiles of each logic tile of the plurality of logic tiles, concurrently performing a first test sequence on each logic tile of the plurality of logic tiles when the field programmable gate array is in the test mode;

concurrently writing second configuration test data into the plurality of the reconfiqurable building block I/O logic of each logic tile of the plurality of logic tiles, when the field programmable gate array is in the test mode, by:

concurrently providing second configuration test data to the at least one data input of the plurality of reconfiqurable building block I/O logic of each logic tile of the plurality of logic tiles; and

after concurrently writing second configuration test data into the plurality of reconfigurable building block I/O logic of each logic tile of the plurality of logic tiles of each logic tile of the plurality of logic tiles, concurrently performing a second test sequence on each logic tile of the plurality of logic tiles when the field programmable gate array is in the test mode.

14. The method of claim 13 wherein:

providing a test mode command to each logic tile of the plurality of logic tiles includes concurrently providing the test mode command to each logic tile of the plurality of logic tiles to configure each logic tile of the plurality of logic tiles for test.

15. The method of claim 13 further including:

reading-back test data from the plurality of logic tiles, (i) when the field programmable gate array is in the test mode and (ii) before performing the test sequence, to verify the first configuration test data concurrently written into the plurality of bitcells of each logic tile of the plurality of logic tiles.

16. The method of claim 13 further including:

electrically isolating each logic tile from the other logic tiles of the plurality of logic tiles when the field programmable gate array is in the test mode.

17. The method of claim 16 wherein:

electrically isolating each logic tile from the other logic tiles of the plurality of logic tiles when the field programmable gate array is in the test mode includes electrically isolating the interconnect network of each logic tile from the interconnect networks of the other logic tiles of the plurality of logic tiles.

18. The method of claim 16 wherein:

electrically isolating each logic tile from each of the other logic tiles of the plurality of logic tiles when the field programmable gate array is in the test mode includes electrically isolating the plurality of reconfigurable building block I/O logic of each logic tile from (i) circuitry of other logic tiles of the plurality of logic tiles and/or (ii) circuitry external to each logic tile of the plurality of logic tiles.

19. The method of claim 16 wherein:

electrically isolating each logic tile from each of the other logic tiles of the plurality of logic tiles when the field programmable gate array is in the test mode includes electrically isolating:

the interconnect network of each logic tile from the interconnect network of each of the other logic tiles of the plurality of logic tiles, and

the plurality of reconfigurable building block I/O logic of each logic tile from (i) circuitry of other logic tiles of the plurality of logic tiles and/or (ii) circuitry external to each logic tile of the plurality of logic tiles.

20. The method of claim 13 further including:

reading-back test data from the plurality of logic tiles, (i) when the field programmable gate array is in the test mode and (ii) before performing the test sequence, to verify the second configuration test data concurrently written into plurality of reconfigurable building block I/O logic of each logic tile of the plurality of logic tiles.

21. An integrated circuit comprising:

a field programmable gate array including:

a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one other logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes:

a normal operating mode;

a test mode;

an interconnect network including a plurality of multiplexers, wherein during operation of the field programmable gate array, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one other adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode;

a plurality of reconfigurable building block I/O logic; and

isolation circuitry, located at an input to each reconfigurable building block I/O logic of the plurality of reconfigurable building block I/O logic of the logic tile, configurable to responsively disconnect the input to the reconfigurable building block I/O logic of the logic tile from circuitry external to the logic tile in the test mode to thereby electrically disconnect the reconfigurable building block I/O logic from circuitry external to the logic tile in the test mode wherein:

the isolation circuitry includes one or more multiplexers, wherein each multiplexer of the isolation circuitry includes: (i) a first input connected to circuitry external to associated logic tile and (ii) a second input connected to an output from the associated reconfigurable building block I/O logic of the associated logic tile.

22. The integrated circuit of claim 21 wherein:

each multiplexer of the isolation circuitry, in the test mode, is capable of connecting an output from the associated reconfigurable building block I/O logic of the associated logic tile to its output.

23. The integrated circuit of claim 21 further including:

test mode control circuitry wherein the isolation circuitry is responsive to one or more control signals from the test mode control circuitry.

24. The integrated circuit of claim 23 wherein:

the test mode control circuitry is capable of concurrently issuing one or more control signals to the isolation circuitry of each of the logic tiles of the plurality of logic tiles wherein, in response, each logic tile is in the test mode.