Modular field programmable gate array, and method of configuring and operating same

1. An integrated circuit comprising:

a bus;

a processor, wherein the processor is connected to the bus; and

programmable/configurable logic circuitry having a periphery, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:

a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:

each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry, and

the first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide data communication between the processor and the plurality of logic tiles; and

wherein the bus is routed between each of the plurality of rows of logic tiles of the plurality of logic tiles.

2. The integrated circuit of claim 1 wherein:

the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles.

3. The integrated circuit of claim 1 wherein:

the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles.

4. The integrated circuit of claim 1 wherein:

the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles.

5. The integrated circuit of claim 1 wherein:

the processor is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture.

6. An integrated circuit comprising:

a multi-drop bus;

a processor, wherein the processor is connected to the multi-drop bus; and

programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, and wherein:

each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein:

a first portion of the plurality of I/Os of the plurality of logic tiles are located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry, and

a second portion of the I/Os of a subset of the plurality of logic tiles are located on a perimeter of the logic tiles that is located on the periphery of the programmable/configurable logic circuitry; and

wherein the multi-drop bus is:

routed between each of the plurality of rows or each of the plurality of columns of logic tiles of the plurality of logic tiles, and

directly connected to a plurality of the first portion of I/Os of each logic tile of the plurality of logic tiles to provide data communication between the processor and the plurality of logic tiles.

7. The integrated circuit of claim 6 wherein:

the processor is configurable to programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture.

8. The integrated circuit of claim 6 wherein:

the second portion of the I/Os of a subset of the plurality of logic tiles are configurable to provide direct communication to circuitry external to the programmable/configurable logic circuitry.

9. The integrated circuit of claim 6 further including:

a plurality of block random access memories, wherein each logic tile of the plurality of logic tiles is directly connected to and associated with a unique block random access memory.

10. The integrated circuit of claim 9 further including:

a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:

the memory bus is configurable to provide direct communication with each block random access memory during operation of the programmable/configurable logic circuitry.

11. The integrated circuit of claim 10 wherein:

each block random access memory of the plurality of block random access memories includes dual-port memory for direct access from the memory bus and by circuitry of the associated logic tile.

12. The integrated circuit of claim 6 further including:

a plurality of block random access memories, wherein each block random access memory is adjacent and directly connected to a logic tile of the plurality of logic tiles.

13. The integrated circuit of claim 12 further including:

a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:

the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry.

14. The integrated circuit of claim 12 further including:

a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is a point-to-point bus.

15. An integrated circuit comprising:

a bus;

a processor, wherein the processor is connected to the bus; and

programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, wherein:

each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein a first portion of the plurality of I/Os of the plurality of the logic tiles are located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry wherein a plurality of the first portion of I/Os directly connect to the bus to provide data communication to/from the processor, and

wherein the bus is:

connected to a plurality of block random access memories, wherein each block random access memory is directly connected to and associated with a logic tile of the plurality of logic tiles, and

routed between (i) a plurality of rows of logic tiles of the plurality of logic tiles or (ii) a plurality of columns of logic tiles of the plurality of logic tiles.

16. The integrated circuit of claim 15 further including:

a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry.

17. The integrated circuit of claim 15 wherein:

the processor is programmable to transmit re-configuration data to each logic tile of the first plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture.

18. The integrated circuit of claim 15 wherein:

the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to at least a subset of the plurality of logic tiles.

19. The integrated circuit of claim 15 wherein:

the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to at least a subset of the plurality of logic tiles.

20. An integrated circuit comprising:

a bus;

a processor, wherein the processor is connected to the bus;

programmable/configurable logic circuitry having a periphery, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:

a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:

each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry, and

the first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide data communication between the processor and the plurality of logic tiles; and

wherein the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles.

21. The integrated circuit of claim 20 wherein:

the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles.

22. The integrated circuit of claim 20 wherein:

the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles.

23. The integrated circuit of claim 20 wherein:

the processor is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture.