Memory device and manufacturing method thereof
There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. The method may include forming a plurality of vertical holes by etching a portion of the stack structure. The method may include forming a memory layer and a channel layer along internal surfaces of the vertical holes. The method may include forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes. The method may include exposing a portion of the channel layer and the first conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer. The method may include forming another conductive layer along surfaces of the exposed portion of the channel layer and the first conductive layer. The method may include forming a slit insulating layer in the slit trench.
1. A memory device comprising:
a source line, including a plurality of conductive layers stacked on each other, formed on a substrate, wherein the source line includes a first source line and a second source line stacked on the first source line, wherein an upper surface of the second source line has an uneven structure;
a plurality of memory cell strings formed over the source line;
a slit trench formed between the memory cell strings; and
a slit insulating layer formed to fill at least a portion of the slit trench.
2. The memory device of claim 1 , wherein the source line is formed horizontally with respect to the substrate.
3. The memory device of claim 1 , wherein the slit trench is formed between some adjacent memory cell strings.
4. The memory device of claim 1 , wherein the slit trench is perpendicular to the substrate.
5. The memory device of claim 1 , wherein each of the memory cell strings includes a memory layer and a channel layer.
6. The memory device of claim 5 , wherein the source line is connected to a lower portion of the channel layer.
7. A memory device comprising:
a first source line and a second source line formed over a substrate, wherein an upper surface of the first source line is flat, wherein the second source line is stacked on the first source line, and has an uneven upper surface;
a stack structure formed over the first source line;
a plurality of vertical holes vertically penetrating the stack structure;
memory layers formed along surfaces of the vertical holes;
channel layers formed along surfaces of the memory layers;
a slit trench formed between the vertical holes; and
a slit insulating layer formed in the slit trench.
8. The memory device of claim 7 , wherein the stack structure includes alternately stacked conductive layers and interlayer insulating layers.
9. The memory device of claim 7 , wherein the vertical holes and the slit trench are perpendicular to the first source line.
10. The memory device of claim 7 , wherein lower portions of the channel layers are coupled to lower surfaces of the second source line.
11. The memory device of claim 7 , further comprising a third source line formed between the second source line and the stack structure.
12. The memory device of claim 11 , wherein the vertical holes penetrate the third source line, and the slit trench is formed over the third source line.
13. The memory device of claim 11 , wherein the channel layers penetrate the third source line, and the memory layers are formed over the third source line.
14. The memory device of claim 13 , wherein a portion of the memory layers are formed between the third source line and the channel layers.