Semiconductor device
A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.
1. A semiconductor device, comprising:
gate electrodes vertically stacked on a substrate; and
channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area, wherein:
the gate dielectric layer is formed of a plurality of layers, the plurality of layers including a tunneling layer, a charge storage layer, and a blocking layer, sequentially disposed on the channel area, and
at least two layers among the tunneling layer, the charge storage layer, and the blocking layer have different thicknesses in different locations.
2. The semiconductor device as claimed in claim 1 , wherein, in at least one layer among the plurality of layers, variations in radius of curvature of an outer circumference is greater than variations in radius of curvature of an inner circumference.
3. The semiconductor device as claimed in claim 1 , wherein each of the tunneling layer, the charge storage layer, and the blocking layer has an inner circumference having greater circularity than an outer circumference.
4. The semiconductor device as claimed in claim 1 , wherein outer circumferences become more circular toward the tunneling layer from the blocking layer.
5. The semiconductor device as claimed in claim 1 , wherein the gate dielectric layer further includes an additional blocking layer disposed outwardly of the blocking layer and having a shape corresponding to the channel hole.
6. The semiconductor device as claimed in claim 1 , wherein at least one layer among the plurality of layers has a rounded corner formed by a side surface and a lower surface at a lower end of the channel area.
7. The semiconductor device as claimed in claim 6 , wherein the outermost layer among the plurality of layers disposed outwardly of the channel hole includes a first surface facing outwardly from the channel hole and in which a side surface and a lower surface are perpendicularly connected, and a second surface facing inwardly from the channel hole and in which a side surface and a lower surface are roundedly connected.
8. The semiconductor device as claimed in claim 1 , wherein a thickness of the channel area is substantially uniform along a circumference of the channel hole.
9. The semiconductor device as claimed in claim 1 , wherein an inner circumference of the channel area has greater circularity than an outer circumference of the channel area.
10. The semiconductor device as claimed in claim 1 , wherein each of the channel holes configure one memory cell string.
11. A semiconductor device, comprising:
gate electrodes vertically stacked on a substrate; and
channel holes passing through the gate electrodes to extend perpendicularly to the substrate, each of the channel holes including a plurality of layers,
wherein an outer circumference and an inner circumference of at least two layers among the plurality of layers have different shapes, and the inner circumference has greater circularity than the outer circumference.
12. The semiconductor device as claimed in claim 11 , wherein the outer circumference and the inner circumference do not have shapes corresponding to each other.
13. The semiconductor device as claimed in claim 11 , wherein variation in radius of curvature of the outer circumference is greater than variation in radius of curvature of the inner circumference.
14. The semiconductor device as claimed in claim 11 , wherein the plurality of layers include a gate dielectric layer and a channel area.
15. A semiconductor device, comprising:
a substrate having a plurality of transistors stacked substantially vertically with respect to the substrate and sharing a single channel structure, the channel structure being oriented substantially vertically with respect to the substrate, the plurality of transistors including:
a plurality of gate electrodes;
a dielectric area that includes at least two insulating layers in contact with one another and extending through each of the plurality of gate electrodes, the dielectric area having an outer circumference and an inner circumference, the outer circumference of the dielectric area having a different shape than the inner circumference of the dielectric area, and the inner circumference of the dielectric area being only convex relative to a vertical axis of the channel structure; and
a channel area that extends through each of the plurality of gate electrodes, the channel area being surrounded by the dielectric area, an outer circumference of the channel area being only convex relative to the vertical axis.
16. The semiconductor device as claimed in claim 15 , wherein the dielectric area includes a tunneling layer, a charge storage layer, and a blocking layer, an outer circumference of the blocking layer being proximate to a gate electrode of the plurality of gate electrodes.
17. The semiconductor device as claimed in claim 16 , wherein the outer circumference of the blocking layer forms the outer circumference of the dielectric area, and the outer circumference of the blocking layer includes at least one concave portion and at least one convex portion relative to the vertical axis.
18. The semiconductor device as claimed in claim 17 , wherein:
the channel area includes a semiconductor material having an outer circumference that is only convex relative to the vertical axis.
19. The semiconductor device as claimed in claim 17 , wherein an inner circumference of the blocking layer has at least one concave portion and at least one convex portion relative to the vertical axis.