Programmable protocol independent bar memory for SSD controller

1. A memory system, comprising:

a programmable bit controller configured to define read-write properties to locations in a base address register (BAR) memory;

a read-write switch configured to:

receive a memory access request;

identify whether the memory access request is a read access or a write access; and

control routing of the memory access request for further processing based on the identify operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory; and

an access controller configured to:

receive the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access;

determine a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access;

bypass the write access when the read-write property is determined to be the first read-write property; and

process the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties.

2. The memory system of claim 1 , wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write.

3. The memory system of claim 2 , wherein the access controller is further configured to write 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and to write 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set.

4. The memory system of claim 1 , wherein the access controller is further configured to calculate a destination address of the write access in the BAR memory.

5. The memory system of claim 1 , wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter.

6. A method, comprising:

defining, with a programmable bit controller, read-write properties to locations in a base address register (BAR) memory;

receiving, with a read-write switch, a memory access request;

identifying, with the read-write switch, whether the memory access request is a read access or a write access;

controlling, with the read-write switch, routing of the memory access request for further processing based on the identifying operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory;

receiving, with an access controller, the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access;

determining, with the access controller, a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access;

bypass the write access when the read-write property is determined to be the first read-write property; and

processing, with the access controller, the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties.

7. The method of claim 6 , wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write.

8. The method of claim 7 , further comprising writing 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and writing 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set.

9. The method of claim 6 , further comprising calculating a destination address of the write access in the BAR memory.

10. The method of claim 6 , wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter.

11. A memory device, comprising:

a programmable bit controller configured to define read-write properties to locations in a base address register (BAR) memory;

a read-write switch configured to:

receive a memory access request;

identify whether the memory access request is a read access or a write access; and

control routing of the memory access request for further processing based on the identify operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory; and

an access controller configured to:

receive the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access;

determine a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access;

bypass the write access when the read-write property is determined to be the first read-write property; and

process the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties.

12. The memory device of claim 11 , wherein the first read-write property includes read-only, and the other read-write properties include read-write 1 to clear, read-write 1 to set, and read-write.

13. The memory device of claim 12 , wherein the access controller is further configured to write 0 to the BAR memory when the read-write property associated with the write access is read-write 1 to clear, and to write 1 to the BAR memory when the read-write property associated with the write access is read-write 1 to set.

14. The memory device of claim 11 , wherein the controller is further configured to calculate a destination address of the write access in the BAR memory.

15. The memory device of claim 11 , wherein the read-write properties are defined to locations in the BAR memory by a 2-bit parameter.