High performance host queue monitor for PCIE SSD controller
Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.
1. A memory system, comprising:
a plurality of queues;
a queue ready indicator suitable for:
grouping the plurality of queues into a predefined number of queue ranges, each queue of the plurality of queues being placed in a single queue range of the predefined number of queue ranges, each queue range having associated with it a queue range ready signal; and
setting a queue range ready signal to ready when all queues in the queue range associated with the queue range ready signal are ready for processing; and
a queue process sequencer suitable for:
determining a queue range ready for processing based on the queue range ready signals; and
processing a queue within the queue range determined to be ready for processing.
2. The memory system of claim 1 , wherein the queue process sequencer is further suitable for transitioning a queue state machine associated with the processed queue to an idle state.
3. The memory system of claim 1 , further comprising a queue access decoder suitable for receiving transactions from a PCIe bus.
4. The memory system of claim 3 , wherein the queue access decoder is further suitable for filtering out transactions not related to queue management.
5. The memory system of claim 1 , further comprising a plurality of queue state machines, each queue state machine being associated with one of the plurality of queues.
6. The memory system of claim 1 , wherein a number of queues in each queue range is 32.
7. The memory system of claim 1 , wherein a number of queues in each queue range is 64.
8. A method, comprising:
grouping, with a queue ready indicator, a plurality of queues into a predefined number of queue ranges, each queue of the plurality of queues being placed in a single queue range of the predefined number of queue ranges, each queue range having associated with it a queue range ready signal;
setting, with the queue ready indicator, a queue range ready signal to ready when all queues in the queue range associated with the queue range ready signal are ready for processing;
determining, with a queue process sequencer, a queue range ready for processing based on the queue range ready signals; and
processing a queue within the queue range determined to be ready for processing.
9. The method of claim 8 , further comprising transitioning a queue state machine associated with the processed queue to an idle state.
10. The method of claim 8 , further comprising receiving, with a queue access decoder, transactions from a PCIe bus.
11. The method of claim 10 , further comprising filtering, with the queue access decoder, transactions not related to queue management.
12. The method of claim 8 , further comprising a plurality of queue state machines, each queue state machine being associated with one of the plurality of queues.
13. The method of claim 8 , wherein a number of queues in each queue range is 32.
14. The method of claim 8 , wherein a number of queues in each queue range is 64.
15. A memory device, comprising:
a plurality of queues;
a queue ready indicator configured to:
group the plurality of queues into a predefined number of queue ranges, each queue of the plurality of queues being placed in a single queue range of the predefined number of queue ranges, each queue range having associated with it a queue range ready signal; and
set a queue range ready signal to ready when all queues in the queue range associated with the queue range ready signal are ready for processing; and
a queue process sequencer configured to:
determine a queue range ready for processing based on the queue range ready signals; and
process a queue within the queue range determined to be ready for processing.
16. The memory device of claim 15 , wherein the queue process sequencer is further configured to transition a queue state machine associated with the processed queue to an idle state.
17. The memory device of claim 15 , further comprising a queue access decoder configured to receive transactions from a PCIe bus.
18. The memory device of claim 17 , wherein the queue access decoder is further configured to filter out transactions not related to queue management.
19. The memory device of claim 15 , further comprising a plurality of queue state machines, each queue state machine being associated with one of the plurality of queues.
20. The memory device of claim 15 , wherein a number of queues in each queue range is 32.