Display panel, method for controlling display panel and display device
The present disclosure provides a display panel, its controlling method and a display device. The display panel includes a plurality of pixel units, a plurality of gate scanning lines arranged on a display substrate and a plurality of data lines arranged on the display substrate and crossing the gate scanning lines. Each pixel unit includes a data writing module, a driving module and a light-emitting element. The data writing module is configured to apply a data voltage to the driving module under the control of a current-level gate scanning signal, and the driving module is configured to drive the light-emitting element to emit light in accordance with the data voltage. The data writing modules of N adjacent pixel units in an identical row are connected to an identical data line, and N is an integer greater than 1. The data voltage across the data line is applied to the data writing modules of the N adjacent pixel units in a time-division manner under the control of the current-level gate scanning signal.
1. A display panel, comprising a plurality of pixel units, a plurality of gate scanning lines arranged on a display substrate, and a plurality of data lines arranged on the display substrate and crossing the gate scanning lines,
wherein each of the pixel units comprises a data writing circuit, a driving circuit and a light-emitting element;
the data writing circuit is configured to apply a data voltage to the driving circuit under the control of a current-level gate scanning signal, and the driving circuit is configured to drive the light-emitting element to emit light in accordance with the data voltage;
the data writing circuits of N adjacent pixel units in an identical row are connected to an identical data line, and N is an integer greater than 1; and
the data voltage across the data line is applied to the data writing circuits of the N adjacent pixel units in a time-division manner under the control of the current-level gate scanning signal;
the N adjacent pixel units in the identical row comprise a first pixel unit and a second pixel unit;
the first pixel unit includes a first data writing circuit, a first driving circuit, and a first light-emitting element, the first data writing circuit includes a first transistor, the first driving circuit includes a first driving transistor, wherein a gate electrode of the first transistor is configured to receive the current-level gate scanning signal, a first electrode of the first transistor is connected to one of the data lines, a second electrode of the first transistor is connected directly to the first driving transistor, the first driving transistor is connected directly to the first light-emitting element, and the first transistor is not connected directly to the first light-emitting element;
the second pixel unit includes a second data writing circuit, a second driving circuit, and a second light-emitting element, the second data writing circuit includes a second transistor, the second driving circuit includes a second driving transistor, wherein a gate electrode of the second transistor is configured to receive the current-level gate scanning signal, a first electrode of the second transistor is connected to the one of the data lines, a second electrode of the second transistor is connected directly to the second driving transistor, the second driving transistor is connected directly to the second light-emitting element, and the second transistor is not connected directly to the second light-emitting element; and
the second pixel unit and the second pixel unit are located in an identical row.
2. The display panel according to claim 1 , wherein N is 2; and
at a stage within each display period, the first transistor and the second transistor are turned on in the time-division manner under the control of the current-level gate scanning signal.
3. The display panel according to claim 2 , wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor.
4. The display panel according to claim 3 , wherein the light-emitting element comprises an OLED.
5. The display panel according to claim 2 , wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
6. The display panel according to claim 2 , wherein a data writing circuit of a pixel unit in an m th row and a (2n+1) th column and a data writing circuit of a pixel unit in the m th row and a (2n+2) th column are connected to an n th data line and configured to receive a data voltage across the n th data line in the time-division manner, m is a positive integer within a range from 1 to A, n is a positive integer within a range from 1 to B, A and B are both positive integers, A is equal to the number of the plurality of gate scanning lines, and 2B+2 is equal to the number of the plurality of data lines.
7. The display panel according to claim 2 , wherein the light-emitting element comprises an OLED.
8. A method for controlling the display panel according to claim 2 , comprising a step of: at the data writing stage within each display period, turning on the first transistor and the second transistor in the time-division manner, so as to apply the data voltage across the data line to the first pixel unit and the second pixel unit in the time-division manner.
9. The display panel according to claim 1 , wherein the light-emitting element comprises an organic light-emitting diode (OLED).
10. The display panel according to claim 1 , wherein each of the pixel units further comprises a storage capacitor, the driving circuit of the pixel unit includes a driving transistor, and the storage capacitor is connected between a gate electrode and a first electrode of the driving transistor.
11. A method for controlling the display panel according to claim 1 , comprising a step of: applying the data voltage across the data line to the data writing circuits of the N adjacent pixel units in the time-division manner under the control of the current-level gate scanning signal, wherein the N adjacent pixel units are in the identical row and connected to the data line, and N is an integer greater than 1.
12. A display device comprising the display panel according to claim 1 .
13. The display device according to claim 12 , wherein N is 2; and
at a stage within each display period, the first transistor and the second transistor are turned on in the time-division manner under the control of the current-level gate scanning signal.
14. The display device according to claim 13 , wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor.
15. The display device according to claim 14 , wherein the light-emitting element comprises an OLED.
16. The display device according to claim 13 , wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
17. The display device according to claim 13 , wherein a data writing circuit of a pixel unit in an m th row and a (2n+1) th column and a data writing circuit of a pixel unit in an m th row and a (2n+2) th column are connected to an n th data line and configured to receive a data voltage across the n th data line in the time-division manner, m is a positive integer within a range from 1 to A, n is a positive integer within a range from 1 to B, A and B are both positive integers, A is equal to the number of the plurality of gate scanning lines, and 2B+2 is equal to the number of the plurality of data lines.
18. The display device according to claim 13 , wherein the light-emitting element comprises an OLED.
19. The display device according to claim 12 , wherein the light-emitting element comprises an OLED.
20. The display device according to claim 12 , wherein each of the pixel units further comprises a storage capacitor, the driving circuit of the pixel unit includes a driving transistor, and the storage capacitor is connected between a gate electrode and a first electrode of the driving transistor.