Ethernet over a reduced number of twisted pair channels

1. An Ethernet transceiver comprising:

transmit circuitry including

a forward error correction (FEC) encoder to encode data into FEC frames,

a modulator to modulate the FEC frames into symbols,

a precoder to equalize the symbols to generate equalized symbols, and

a transmitter to transmit the equalized symbols over a reduced number of channels N S with respect to a baseline number of channels N 0 ;

wherein for a reduced data rate B S with respect to a baseline data rate B 0 , the FEC frames are assembled by the FEC encoder to exhibit an expanded frame time FT S that is expanded from a baseline frame time FT 0 by a factor of B 0 /B S ; and

wherein for the reduced data rate B S , the modulator generates reduced rate symbols of a reduced symbol rate SR S that are transmitted by the transmitter at the reduced symbol rate SR S that is reduced from a baseline symbol rate SR 0 by a factor of (B 0 *N S )/(B S *N 0 ).

2. The Ethernet transceiver according to claim 1 , wherein:

the baseline number of channels N 0 four;

the baseline data rate B 0 is 10 Gbps;

the baseline symbol rate SR 0 is 800 MHz; and

the baseline frame time FT 0 is 320 nanoseconds.

3. The Ethernet transceiver according to claim 1 , wherein the reduced number of channels N S is two.

4. The Ethernet transceiver according to claim 1 , wherein the reduced number of channels N S is one.

5. The Ethernet transceiver according to claim 1 , wherein ones of the reduced numbers of channels comprises a twisted-pair copper channel.

6. The Ethernet transceiver according to claim 1 , wherein the symbols comprise one from the group including PAM16, DSQ128, SQ64, PAM8, DSQ32, SQ16 and PAM4.

7. The Ethernet transceiver according to claim 1 , wherein the reduced rate symbols transmitted at the reduced symbol rate SR S are of the same modulation type as the symbols transmitted at the baseline symbol rate SR 0 .

8. The Ethernet transceiver according to claim 1 , wherein the reduced rate symbols transmitted at the reduced symbol rate SR S are of a different modulation type as the symbols transmitted at the baseline symbol rate SR 0 .

9. The Ethernet transceiver according to claim 1 , further comprising:

receiver circuitry including

a demodulator to demodulate received symbols, and

an FEC decoder.

10. An Ethernet transceiver comprising:

transmit circuitry including

a forward error correction (FEC) encoder to encode data into FEC frames,

a modulator to modulate the FEC frames into symbols,

a precoder to equalize the symbols to generate equalized symbols, and

a transmitter to transmit the equalized symbols over a selected number of channels;

wherein dining a baseline mode of operation, the Ethernet transceiver operates to assemble the FEC frames to exhibit a baseline frame time FT 0 , to transmit baseline symbols at a baseline symbol rate SR 0 along a baseline number of channels N 0 for a baseline data rate B 0 ;

wherein during a reduced-pairs mode of operation, the Ethernet transceiver operates to assemble the FEC frames as expanded FEC frames to exhibit an expanded frame time FT S , to transmit data at a reduced data rate B S by transmitting reduced rate symbols of a reduced symbol rate SR S along a reduced number of channels N S ;

wherein for the reduced data rate B S with respect to the baseline data rate B 0 , the expanded FEC frames are assembled by the EEC encoder to exhibit the expanded frame time FT S that is expanded from the baseline frame time FT 0 by a factor of B 0 /B S ; and

wherein for the reduced data rate B S , the reduced symbol rate SR S is reduced from the baseline symbol rate SR S by a factor of (B 0 *N S )/B S *N 0 ).

11. The Ethernet transceiver according to claim 10 , wherein:

the baseline number of channels N 0 is four;

the baseline data rate B 0 is 10 Gbps;

the baseline symbol rate SR 0 is 800 MHz; and

the baseline frame time FT 0 is 320 nanoseconds.

12. The Ethernet transceiver according to claim 10 , wherein the reduced number of channels N S is two.

13. The Ethernet transceiver according to claim 10 , wherein the reduced number of channels N S is one.

14. The Ethernet transceiver according to claim 10 , wherein ones of the reduced number of channels comprises a twisted-pair copper channel.

15. The Ethernet transceiver according to claim 10 , wherein the symbols comprise one from the group including PAM16, DSQ128, DSQ64, PAM8, DSQ32, SQ16 and PAM4.

16. The Ethernet transceiver according to claim 10 , wherein the reduced rate symbols transmitted at the reduced symbol rate SR S are of the same modulation type as the symbols transmitted at the baseline symbol rate SR 0 .

17. The Ethernet transceiver according to claim 10 , wherein the reduced rate symbols transmitted at the reduced symbol rate SR S are of a different modulation type as the symbols transmitted at the baseline symbol rate SR 0 .

18. A method of operation in an Ethernet transceiver IC chip, the method comprising:

transmitting data including

encoding data into FEC frames with an FEC encoder,

modulating the FEC frames into symbols with a modulator,

equalizing the symbols with a precoder to generate equalized symbols, and

transmitting the equalized symbols over a reduced number of channels N S with respect to a baseline number of channels N 0 ;

wherein for a reduced data rate B S with respect to a baseline data rate B 0 , the encoding includes assembling the FEC frames to exhibit an expanded frame time FT S that is expanded from a baseline frame time FT 0 by a factor of B 0 /B S ; and

wherein the transmitting of the equalized symbols is carried out at a symbol rate SR S that is reduced from a baseline symbol rate SR 0 by a factor of (B 0 *N S )/(B S *N 0 ).