IP Library › Granted Patent US 10,044,269
Granted Patent B2
US 10,044,269 · App. 15/224,788 · Granted Aug 7, 2018

Switching converter with improved recovery time

Inventors: Yu-Ta Lin (New Taipei, TW); Yuan-Wen Hsiao (Hsinchu, TW)
Assignee: Dialog Semiconductor (UK) Limited
H02M3/158G05F3/262
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Quick Facts
Patent No.
US 10,044,269
App. No.
15/224,788
Granted
Aug 7, 2018
Kind
B2
Abstract

A switching converter, which produces an output voltage, contains a switch operable between a first state for opposing a decrease in the output voltage and a second state for opposing an increase in the output voltage. The converter also contains a circuit adapted to determine a time period during which the output voltage is decreasing, wherein during the time period the switch is in the first state. The circuit also calculates, based on the time period, a time to turn the switch from the first state to the second state to prevent the output voltage increasing above a reference value. Optionally, the time to turn the switch to the second state is based on a duty cycle of the converter.

Claims (48)

1. A converter for outputting an output voltage comprising

a switch operable between a first state for opposing a decrease in the output voltage and a second state for opposing an increase in the output voltage; and

a circuit adapted

to determine a time period during which the output voltage keeps decreasing, wherein during the time period the switch is in the first state; and

to calculate a time to turn the switch from the first state to the second state to prevent the output voltage increasing above a reference value;

wherein the converter has a duty cycle, and wherein the time to turn the switch to the second state is based on a product of a square root of the duty cycle and the time period.

2. The converter as claimed in claim 1 , wherein the circuit comprises a memory device coupled to the switch, the memory device having a first input coupled to a first circuit, a second input coupled to a second circuit, and an output to output a signal to turn the switch to the second state.

3. The converter as claimed in claim 2 , wherein the first circuit is adapted to detect a gradient of the output voltage, and to output a first signal proportional to the time period based on the gradient.

4. The converter as claimed in claim 3 , wherein the first circuit comprises

a first comparator adapted to detect a negative gradient of the output voltage;

a second comparator adapted to detect a positive gradient of the output voltage; and

a memory device comprising a first input coupled to an output of the first comparator, a second input coupled to an output of the second comparator, and an output to output a signal proportional to the time period.

5. The converter as claimed in claim 2 , wherein the second circuit comprises an input for receiving a signal proportional to the time period and an output to output a signal proportional to another time period based on the duty cycle of the converter.

6. The converter as claimed in claim 5 , wherein the second circuit comprises

a current generator,

a capacitor coupled to the current generator, and

a comparator having an input coupled to the capacitor and an output coupled to a logic gate;

wherein the current generator is adapted to output a current to control a rate of discharge of the capacitor.

7. The converter as claimed in claim 6 , wherein the current generator is adapted to output a current proportional to a square root of an input current.

8. The converter as claimed in claim 7 , wherein the current generator comprises

an input current generator for generating the input current;

an operational amplifier adapted to control an output switch; and

a current mirror coupled to an input of the operational amplifier.

9. The converter as claimed in claim 8 , wherein the current mirror comprises a first transistor and a second transistor, and wherein a size of the second transistor is four times as large as a size of the first transistor.

10. The converter as claimed in claim 6 , wherein the current generator is adapted to output a current proportional to an inverse of a square root of the duty cycle.

11. The converter as claimed in claim 6 , wherein the current generator comprises a digital circuit adapted to receive a voltage value and to generate a digital value proportional to an inverse of a square root of the voltage value.

12. A method of regulating an output voltage of a converter comprising:

providing a switch operable between a first state for opposing a decrease in the output voltage and a second state for opposing an increase in the output voltage;

determining a time period during which the output voltage keeps decreasing, wherein during the time period the switch is in the first state;

calculating a time to turn the switch from the first state to the second state to prevent the output voltage increasing above a reference value; wherein the converter has a duty cycle, and wherein the time to turn the switch to the second state is based on a product of a square root of the duty cycle and the time period; and

switching the switch to the second state at the calculated time.

13. The method as claimed in claim 12 , wherein detecting the time period comprises detecting a gradient of the output voltage.

14. The method as claimed in claim 13 , wherein detecting a gradient comprises detecting a negative gradient of the output voltage and detecting a positive gradient of the output voltage.

15. The method as claimed in claim 12 , wherein calculating the time comprises generating a current proportional to a square root of an input current.

16. The method as claimed in claim 15 , wherein the current generator comprises

an input current generator for generating the input current;

an operational amplifier adapted to control an output switch; and

a current mirror coupled to an input of the operational amplifier.

17. The method as claimed in claim 16 , wherein the current mirror comprises a first transistor and a second transistor, and wherein a size of the second transistor is four times as large as a size of the first transistor.

18. The method as claimed in claim 12 , wherein calculating the time comprises generating a current proportional to an inverse of the square root of the duty cycle.

19. The method as claimed in claim 12 , wherein calculating the time comprises receiving a voltage value and generating a digital value proportional to an inverse of a square root of the voltage value.

20. The method as claimed in claim 12 , wherein the circuit comprises a memory device coupled to the switch, the memory device having a first input coupled to a first circuit, a second input coupled to a second circuit, and an output to output a signal to turn the switch to the second state.

21. The method as claimed in claim 20 , wherein the second circuit comprises an input for receiving a signal proportional to the time period and an output to output a signal proportional to another time period based on the duty cycle of the converter.

22. The method as claimed in claim 21 , wherein the second circuit comprises

a current generator,

a capacitor coupled to the current generator, and

a comparator having an input coupled to the capacitor and an output coupled to a logic gate;

wherein the current generator is adapted to output a current to control a rate of discharge of the capacitor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2018
From: POWERVENTURE SEMICONDUCTOR LIMITED
To: DIALOG SEMICONDUCTOR (UK) LIMITED
Reel/Frame 044985/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2016
From: LIN, YA-TA; HSIAO, YUAN-WEN
To: POWERVENTURE SEMICONDUCTOR LIMITED
Reel/Frame 039786/0799 →
Priority Claims (1)
GB 1607622.6 · Apr 30, 2016 · national
Continuity (1)
Related Publication 20170315578A1 · Nov 2, 2017
Cited By (1)
US 12,712,452