IP Library Granted Patent US 9,530,871
Granted Patent B1
US 9,530,871 · App. 15/225,836 · Granted Dec 27, 2016

Method for fabricating a semiconductor device

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Quick Facts
Patent No.
US 9,530,871
App. No.
15/225,836
Granted
Dec 27, 2016
Kind
B1
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Claims (21)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a fin-shaped structure thereon;

forming an epitaxial layer on the fin-shaped structure;

forming a first contact etch stop layer (CESL) on the epitaxial layer;

forming a source/drain region in the epitaxial layer; and

forming a second CESL after forming the source/drain region.

2. The method of claim 1 , further comprising a shallow trench isolation (STI) around the fin-shaped structure, the method comprises:

forming a spacer adjacent to the fin-shaped structure;

removing part of the fin-shaped structure;

forming the epitaxial layer on the fin-shaped structure;

forming the first CESL on the epitaxial layer, the spacer, and the STI;

forming a first cap layer on the first CESL;

forming the source/drain region in the epitaxial layer; and

forming the second CESL on the first cap layer.

3. The method of claim 2 , wherein the first cap layer comprises SiON or SiCON.

4. The method of claim 2 , further comprising forming a second cap layer on the epitaxial layer before forming the first CESL.

5. The method of claim 4 , wherein the second cap layer comprises SiO 2 .

6. The method of claim 1 , wherein the first CESL and the second CESL comprise same material.

7. The method of claim 1 , wherein the first CESL and the second CESL comprise SiCN or SiN.

8. The method of claim 1 , wherein the first CESL and the second CESL comprise same thickness.

9. The method of claim 1 , further comprising performing an anneal process after forming the source/drain region and before forming the second CESL.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2016
From: TSAI, MING-YUEH; FANG, JIA-FENG; CHEN, YI-WEI; JHANG, JING-YIN; LEE, RUNG-YUAN; WENG, CHEN-YI; WU, WEI-JEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039308/0693 →