IP Library › Granted Patent US 9,698,094
Granted Patent B2
US 9,698,094 · App. 15/228,059 · Granted Jul 4, 2017

Wiring board and electronic component device

Inventors: Hiroharu Yanagisawa (Nagano, JP); Kazuhiro Kobayashi (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49838H01L21/486H01L21/4853H01L21/563H01L23/3178H01L23/49827H01L24/16H05K1/0213H05K1/111H05K1/181H01L2224/16227
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Quick Facts
Patent No.
US 9,698,094
App. No.
15/228,059
Granted
Jul 4, 2017
Kind
B2
Abstract

A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.

Claims (16)

1. A wiring board comprising:

an insulating layer; and

a wiring layer comprising: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer,

wherein a recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and

the recess portion is filled with the insulating layer.

2. The wiring board according to claim 1 , wherein the height of the upper surface of the wiring layer is lower than that of an upper surface of the insulating layer.

3. The wiring board according to claim 1 , wherein the wiring layer consists of an electrolytic metal plating layer, and the side surface and lower surface of the wiring layer are roughened.

4. The wiring board according to claim 1 , wherein

the wiring layer further comprises a pad configured to be connected to a terminal of an electronic component.

5. The wiring board according to claim 1 , wherein the recess portion is fully filled with the insulating layer.

6. The wiring board according to claim 1 , wherein the recess portion is formed in the whole of the outer edge portion of the upper surface of the wiring layer.

7. The wiring board according to claim 1 , wherein a peripheral edge portion of the upper surface of the wiring layer is covered with the insulating layer.

8. The wiring board according to claim 1 , wherein an opening portion is formed in a lower surface of the insulating layer such that a portion of the lower surface of the wiring layer is exposed through the opening portion, and the exposed portion of the lower surface of the wiring layer is configured as an external connection pad.

9. An electronic component device comprising:

the wiring board according to claim 1 ; and

an electronic component having a terminal, wherein the terminal is connected to the upper surface of the wiring layer of the wiring board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2016
From: YANAGISAWA, HIROHARU; KOBAYASHI, KAZUHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 039341/0700 →
Priority Claims (2)
JP 2015-155697 · Aug 6, 2015 · national
JP 2016-142613 · Jul 20, 2016 · national
Continuity (1)
Related Publication 20170040249A1 · Feb 9, 2017