Semiconductor memory device and manufacturing the same
View Patent ↗One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor substrate. The conducting layers are disposed in a laminating direction. Each of the plurality of the conducting layers is connected to each of the plurality of the memory cells. Each conducting layer has a structure where a first conductive film and a second conductive film are laminated in the laminating direction. The conducting layers adjacent to one another in the laminating direction have a laminating order of the first conductive film and the second conductive film different from one another.
1. A semiconductor memory device, comprising:
a plurality of memory cells three-dimensionally disposed on a semiconductor substrate; and
a plurality of conducting layers disposed in a laminating direction, wherein
each of the plurality of the conducting layers is connected to each of the plurality of the memory cells, and has a structure where a first conductive film and a second conductive film are laminated in the laminating direction, and
the conducting layers adjacent to one another in the laminating direction have different laminating orders of the first conductive film and the second conductive film.
2. The semiconductor memory device according to claim 1 , wherein
the first conductive film is a barrier metal film and the second conductive film is a metal film.
3. The semiconductor memory device according to claim 2 , wherein
the conducting layer on a lowermost layer in the laminating direction has a configuration where the barrier metal film is disposed as a lower layer of the conducting layer, and the metal film is disposed as an upper layer of the conducting layer.
4. The semiconductor memory device according to claim 2 , wherein
the conducting layer on an uppermost layer in the laminating direction has a configuration where the metal film is disposed as a lower layer of the conducting layer, and the barrier metal film is disposed as an upper layer of the conducting layer.
5. The semiconductor memory device according to claim 2 , wherein
the barrier metal film is constituted of metal nitride.
6. The semiconductor memory device according to claim 2 , wherein
the conducting layer with the barrier metal film as a lower layer and the metal film as an upper layer, and the conducting layer with the metal film as a lower layer and the barrier metal film as an upper layer are disposed in an identical number.
7. The semiconductor memory device according to claim 1 , further comprising:
a semiconductor layer extending in the laminating direction, the semiconductor layer functioning as a channel body of the memory cell.
8. The semiconductor memory device according to claim 7 , wherein
the semiconductor layer includes a core semiconductor layer on an upper portion of the semiconductor layer.
9. The semiconductor memory device according to claim 8 , wherein
the core semiconductor layer is constituted of amorphous silicon.
10. The semiconductor memory device according to claim 1 , wherein
the conducting layer on an uppermost layer has an upper surface covered with a cover film.
11. The semiconductor memory device according to claim 1 , wherein
the memory cell includes an electric charge accumulating layer.
12. The semiconductor memory device according to claim 1 , wherein
the plurality of conducting layers includes interlayer insulating layers between the conducting layers, and
the interlayer insulating layers adjacent to one another in a laminating direction are constituted of identical material, and are different in physical structures of surfaces thereof.
13. The semiconductor memory device according to claim 1 , further comprising:
a source contact extending in the laminating direction, wherein
the source contact has a tapered shape in which a diameter increases with separating away from the semiconductor substrate.
14. The semiconductor memory device according to claim 13 , wherein
the source contact has a structure where a plurality of parts with the tapered shape are laminated.
15. The semiconductor memory device according to claim 1 , wherein
each of the plurality of the conducting layers functions as a word line.
16. The semiconductor memory device according to claim 1 , wherein
the plurality of the conducting layers disposed in the laminating direction include two first conductive films opposing one another, with respect to one interlayer insulating layer formed therebetween, and two second conductive films opposing one another, with respect to another interlayer insulating layer formed therebetween, repeatedly laminated in alternation in the laminating direction.
17. The semiconductor memory device according to claim 1 , wherein
each of the plurality of memory cells includes block layer, and
each of the block layers contacts with both of the first conductive film and the second conductive film.
18. A method for manufacturing a semiconductor memory device, wherein
the semiconductor memory device includes a plurality of memory cells and a plurality of conducting layers, the plurality of memory cells being three-dimensionally disposed on a semiconductor substrate, the plurality of conducting layers being disposed in a laminating direction, and the plurality of conducting layers being connected to the plurality of the memory cells, and
the manufacturing method comprises:
alternately laminating a plurality of first interlayer insulating layers and sacrificial films in a laminating direction on the semiconductor substrate;
forming a support pillar that passes through the plurality of the first interlayer insulating layers and the sacrificial films;
forming a first hole that passes through the plurality of the first interlayer insulating layers and the sacrificial films;
removing the sacrificial film via the first hole to form a void;
forming a first conductive film, a second conductive film, and a second interlayer insulating layer on the inner wall of the void; and
forming a second hole in a region corresponding to the first hole and forming a groove in a region corresponding to the support pillar to remove a part where the first conductive film and the second conductive film extend in the laminating direction, so as to form two layers of the conducting layer.
19. The method for manufacturing the semiconductor memory device according to claim 18 , wherein
the first interlayer insulating layer and the second interlayer insulating layer employ identical material and different film forming methods.
20. The method for manufacturing the semiconductor memory device according to claim 18 , further comprising
forming at least an electric charge accumulating film inside the second hole internally to form the memory cell, and
forming a semiconductor layer as a channel body of the memory cell.
21. The method for manufacturing the semiconductor memory device according to claim 18 , further comprising
forming at least a conductive film inside the groove to form a source contact.