IP Library › Granted Patent US 9,911,831
Granted Patent B2
US 9,911,831 · App. 15/229,665 · Granted Mar 6, 2018

Spacer formation on semiconductor device

Inventors: Thamarai Selvi Devarajan (Albany, NY); Sanjay C. Mehta (Niskayuna, NY); Eric R. Miller (Schenectady, NY); Soon-Cheon Seo (Glenmont, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/66795H01L21/823814H01L21/823821H01L21/823864H01L29/0653H01L29/4238H01L29/66545H01L29/7855
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Quick Facts
Patent No.
US 9,911,831
App. No.
15/229,665
Granted
Mar 6, 2018
Kind
B2
Abstract

A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Claims (30)

1. A method for forming a semiconductor device, the method comprising:

forming a semiconductor fin on a substrate;

forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin;

forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack;

depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack;

depositing a first sacrificial layer on the first liner layer;

removing the first sacrificial layer over the first sacrificial gate stack to expose the first liner layer on the first sacrificial gate stack while retaining the first liner layer on the first sacrificial gate stack and the spacers adjacent to the first sacrificial gate stack; and

growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

2. The method of claim 1 , further comprising:

depositing a second sacrificial layer on the first source drain region, the first sacrificial gate stack and the second sacrificial gate stack;

removing the second sacrificial layer and the first sacrificial layer over the second gate stack; and

growing a second semiconductor material on exposed portions of the fin to form a second source/drain region adjacent to the second gate sacrificial gate stack.

3. The method of claim 1 , further comprising removing exposed portions of the first liner layer after removing the first sacrificial layer over the first gate stack.

4. The method of claim 2 , further comprising removing exposed portions of the first liner layer after removing the second sacrificial layer and the first sacrificial layer over the second gate stack.

5. The method of claim 1 , wherein the first liner layer includes an oxide material.

6. The method of claim 2 , wherein the spacers include a first nitride material, the first sacrificial layer includes a second nitride material, and the second sacrificial layer includes the second nitride material.

7. The method of claim 6 , wherein the first nitride material is different from the second nitride material.

8. The method of claim 2 , further comprising:

removing the first sacrificial gate stack and the second sacrificial gate stack to expose the first channel region and the second channel region;

forming a first metal gate stack over the first channel region; and

forming a second metal gate stack over the second channel region.

9. The method of claim 1 , wherein the spacers adjacent to the first sacrificial gate stack and the spacers adjacent to the second sacrificial gate stack have a substantially equal thickness.

10. A method for forming a semiconductor device, the method comprising:

forming a semiconductor fin on a substrate;

forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, wherein the first channel region is a pFET region and the second channel region is an nFET region;

forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, wherein the spacers adjacent to the first sacrificial gate stack and the spacers adjacent to the second sacrificial gate stack have a substantially equal thickness;

depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack;

depositing a first sacrificial layer on the first liner layer;

removing a portion of the first sacrificial layer over the first gate stack to expose a portion the first liner layer on the first sacrificial gate stack; and

growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2021
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 056803/0502 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2016
From: DEVARAJAN, THAMARAI SELVI; MEHTA, SANJAY C.; MILLER, ERIC R.; SEO, SOON-CHEON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039355/0782 →
Continuity (2)
Continuation 14969021 · Dec 15, 2015
Related Publication 20170170301A1 · Jun 15, 2017