Power package module of multiple power chips and method of manufacturing power chip unit
The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.
1. A method of manufacturing a power chip unit, the power chip unit comprising at least two power chips placed in parallel, and the method comprising the following steps performed in sequence:
providing a wafer comprising a plurality of power chips arranged in an array;
attaching a metalized side of the wafer to a film;
turning over the wafer so that an un-metalized side that is opposite to the metalized side of the wafer to be upward;
dicing the un-metalized side of the wafer to form a gap between the power chips so that a distance between the power chips is a width of a dicing blade for dicing the wafer, wherein the width is no more than 200 μm;
coating a bonding part on the un-metalized side of the wafer to fill the bonding part into the gap between the power chips;
thinning the un-metalized side of the wafer to a required thickness;
removing the film from the metalized side and bonding the un-metalized side of the wafer onto another film; and
dicing a part of the bonding part in the wafer to form a plurality of independent power chip units, wherein the power chips in the power chip unit are bonded by the bonding part.
2. The method according to claim 1 , wherein a gap between the power chips is smaller than a preset width.
3. The method according to claim 2 , wherein the preset width is smaller than or equal to 200 μm.
4. The method according to claim 1 , wherein a material of the bonding part has a rigidity more than Shore A10, an insulating strength more than 10 kV/mm, and an electrical resistivity more than 1.0E11 Ω·cm.