Sample and hold circuit
Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.
1. An apparatus, comprising:
a sample and hold circuit including a first capacitor and a second capacitor and configured and arranged to
in a first mode
sample a voltage difference between an input node of the sample and hold circuit and a first reference voltage using the first capacitor; and
provide a voltage stored by the second capacitor, and referenced to a second reference voltage, to a first output node of the sample and hold circuit; and
in a second mode
sample a voltage difference between the input node and the first reference voltage using the second capacitor; and
provide a voltage stored by the first capacitor, and referenced to the second reference voltage, to a second output node of the sample and hold circuit; and
wherein the sample and hold circuit includes a set of components including capacitors and transistors, each component being subject to failure in response to a voltage difference between at least a pair of terminals of the component exceeding the tolerance voltage of the component and the voltage difference between the input node and the second reference voltage is greater than the tolerance voltage of the components.
2. The apparatus of claim 1 , wherein the sample and hold circuit further includes a switching circuit configured and arranged to
in the first mode
connect a first terminal of the first capacitor to the input node, a second terminal of the first capacitor to the first reference voltage, a first terminal of the second capacitor to an output node, and a second terminal of the second capacitor to the second reference voltage;
disconnect the first terminal of the first capacitor from the output node, the second terminal of the first capacitor from the second reference voltage, the first terminal of the second capacitor from the input node, and the second terminal of the second capacitor from the first reference voltage; and
in the second mode
connect the first terminal of the second capacitor to the input node, the second terminal of the second capacitor to the first reference voltage, the first terminal of the first capacitor to the output node, and the second terminal of the first capacitor to the second reference voltage; and
disconnect the first terminal of the second capacitor from the output node, the second terminal of the second capacitor from the second reference voltage, the first terminal of the first capacitor from the input node, and the second terminal of the first capacitor from the first reference voltage.
3. The apparatus of claim 2 , wherein
the switching circuit includes a set of transistors;
a voltage at the first terminal of the first capacitor is used to control one or more of the set of transistors that performs the connecting of the first terminal of the second capacitor to the input node and the connecting of the first terminal of the second capacitor to the output node; and
a voltage at the first terminal of the second capacitor is used to control one or more of the set of transistors that perform the connecting of the first terminal of the first capacitor to the input node and perform the connecting of the first terminal of the first capacitor to the output node.
4. The apparatus of claim 1 , wherein the sample and hold circuit is configured and arranged to operate in the first mode in response to a clock signal having a first value and operate in the second mode in response to the clock signal having a second value.
5. The apparatus of claim 1 , further comprising a control circuit configured and arranged to
disable and initialize the sample and hold circuit in response to a control signal being set to a first value; and
enable the sample and hold circuit in response to the control signal being set to a second value.
6. The apparatus of claim 5 , wherein the control circuit is configured and arranged to disable and initialize the sample and hold circuit by connecting a terminal of one of the first and second capacitors to the first reference voltage.
7. The apparatus of claim 5 , wherein the control circuit includes
a first circuit configured to connect a first terminal of the first capacitor to the second reference node in response to the control signal being set to the first value and the sample and hold circuit operating in the first mode; and
a second circuit configured to connect a first terminal of the first capacitor to the second reference node in response to the control signal being set to the first value and the sample and hold circuit operating in the second mode.
8. The apparatus of claim 1 , wherein
the first reference voltage is Vdd;
the second reference voltage is Vss; and
a voltage of the input node is greater than Vdd.
9. The apparatus of claim 1 , wherein
the first reference voltage is Vss;
the second reference voltage is Vdd; and
a voltage of the input node is less than Vss.
10. A method comprising:
in a first mode, using a switching circuit
connecting a first capacitor to sample a voltage difference between an input node and a first reference voltage using a first capacitor; and
connecting a second capacitor to provide a voltage stored by a second capacitor and referenced to a second reference voltage to a first output node; and
in a second mode, using the switching circuit
connecting the second capacitor to sample a voltage difference between the input node and the first reference voltage; and
connecting the first capacitor to provide a voltage stored by the first capacitor and referenced to the second reference voltage to a second output node; and
wherein the switching circuit includes a set of components including capacitors, transistors or a combination thereof, each component being subject to failure in response to a voltage difference between at least a pair of terminals of the component exceeding the tolerance voltage of the component and the voltage difference between the input node and the second reference voltage is greater than the tolerance voltage of the components.
11. The method of claim 10 , further comprising, using the switching circuit connected to the first and second capacitors,
in the first mode
connecting a first terminal of the first capacitor to the input node, a second terminal of the first capacitor to the first reference voltage, a first terminal of the second capacitor to an output node, and a second terminal of the second capacitor to the second reference voltage; and
disconnecting the first terminal of the first capacitor from the output node, the second terminal of the first capacitor from the second reference voltage, the first terminal of the second capacitor from the input node, and the second terminal of the second capacitor from the first reference voltage; and
in the second mode
connecting the first terminal of the second capacitor to the input node, the second terminal of the second capacitor to the first reference voltage, the first terminal of the first capacitor to the output node, and the second terminal of the first capacitor to the second reference voltage; and
disconnecting the first terminal of the second capacitor from the output node, the second terminal of the second capacitor from the second reference voltage, the first terminal of the first capacitor from the input node, and the second terminal of the first capacitor from the first reference voltage.
12. The method of claim 11 , wherein
the switching circuit includes a set of transistors;
a voltage at the first terminal of the first capacitor is used to control one or more of the set of transistors that performs the connecting of the first terminal of the second capacitor to the input node and the connecting of the first terminal of the second capacitor to the output node; and
a voltage at the first terminal of the second capacitor is used to control one or more of the set of transistors that perform the connecting of the first terminal of the first capacitor to the input node and perform the connecting of the first terminal of the first capacitor to the output node.
13. The method of claim 10 , further comprising
operating in the first mode in response to a clock signal being set to a first value and
operating in the second mode in response to the clock signal being set to a second value.
14. The method of claim 10 , further comprising, using a control circuit coupled to the sample and hold circuit
disabling and initializing the sample and hold circuit in response to a control signal having a first value; and
enabling the sample and hold circuit in response to the control signal having a second value.
15. The method of claim 14 , wherein the disabling and initializing of the sample and hold circuit includes connecting a terminal of one of the first and second capacitors to the first reference voltage.
16. The apparatus of claim 14 , wherein the control circuit includes
a first circuit configured to connect a first terminal of the first capacitor to the second reference node in response to the control signal being set to the first value and the sample and hold circuit operating in the first mode; and
a second circuit configured to connect a first terminal of the first capacitor to the second reference node in response to the control signal being set to the first value and the sample and hold circuit operating in the second mode.
17. The method of claim 10 , wherein
the first reference voltage is Vdd;
the second reference voltage is Vss; and
a voltage of the input node is greater than Vdd.
18. The method of claim 10 , wherein
the first reference voltage is Vss;
the second reference voltage is Vdd; and
a voltage of the input node is less than Vss.