IP Library Granted Patent US 9,972,570
Granted Patent B2
US 9,972,570 · App. 15/232,820 · Granted May 15, 2018

Semiconductor device and method for fabricating the same

Inventors: Ming-Te Wei (Changhua County, TW); Chun-Hsien Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L23/5256H01L21/0332H01L21/31116H01L21/31122H01L21/31138H01L21/7681H01L21/76811H01L21/823475H01L23/5226
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Quick Facts
Patent No.
US 9,972,570
App. No.
15/232,820
Granted
May 15, 2018
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.

Claims (19)

1. A semiconductor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a first conductor in the first dielectric layer, wherein the first conductor is funnel-shaped and the first conductor comprises:

a first portion comprising a first sidewall; and

a second portion embedded in the first dielectric layer, wherein the second portion comprises a second sidewall and a third sidewall, each of the second sidewall and the third sidewall is planar, and a first angle at an intersection of the first sidewall and a horizontal plane is between 80 degrees to 90 degrees, a second angle at the intersection of the second sidewall and the horizontal plane is between 30 degrees to 50 degrees, and a third angle at the intersection of the third sidewall and the horizontal plane is between 85 degrees to 90 degrees.

2. The semiconductor device of claim 1 , further comprising:

a second dielectric layer on the substrate;

a second conductor embedded in the second dielectric layer;

the first dielectric layer on the second dielectric layer; and

the first conductor in the first dielectric layer and contacting the second conductor.

3. The semiconductor device of claim 1 , further comprising a stop layer between the first dielectric layer and the second dielectric layer.

4. The semiconductor device of claim 1 , wherein the first portion is embedded in the stop layer.

5. A semiconductor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a first conductor in the first dielectric layer, wherein a portion of the first conductor is funnel-shaped and the first conductor comprises:

a first portion comprising a first sidewall; and

a second portion embedded in the first dielectric layer, wherein the second portion comprises a second sidewall and a third sidewall, respectively, each of the second sidewall and the third sidewall is planar, the second sidewall is on left sidewall of the second portion and the third sidewall is on right sidewall of the second portion, and a first angle at an intersection of the second sidewall and a horizontal plane is between 40 degrees to 60 degrees, a second angle at the intersection of the third sidewall and the horizontal plane is between 30 degrees to 50 degrees, wherein the first angle is not equal to the second angle, and a third angle at the intersection of the first sidewall of the first portion and the horizontal plane is between 80 degrees to 90 degrees.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: WEI, MING-TE; LIN, CHUN-HSIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039389/0186 →
Priority Claims (1)
CN 2016 1 0555077 · Jul 14, 2016 · national
Continuity (1)
Related Publication 20180019205A1 · Jan 18, 2018