Nonvolatile resistance changing semiconductor memory using first and second writing operations
A nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being connected to the second terminal, and a first driver electrically connected to the control terminal, applying a first potential to the control terminal in a first write operation, and applying a second potential larger than the first potential to the control terminal in a second write operation.
1. A nonvolatile semiconductor memory comprising:
a plurality of resistance-change elements having first terminals and second terminals;
a plurality of transistors having third terminals, fourth terminals and control terminals, the third terminals being connected to the second terminals respectively;
a first driver electrically connected to the control terminals, applying a first potential to the control terminal of one of the transistors in a first write operation, and applying a second potential larger than the first potential to the control terminal of another one of the transistors in a second write operation; and
a second driver electrically connected to the first and fourth terminals, applying a third potential larger than a potential of the fourth terminal of the one of the transistors to the first terminal of one of the resistance-change elements in the first write operation, and applying a fourth potential larger than a potential of the first terminal of another one of the resistance-change elements to the fourth terminal of the another one of the transistors in the second write operation,
wherein the one of the resistance-change elements has first resistance by the first write operation, and the another one of the resistance-change elements has second resistance smaller than the first resistance by the second write operation,
each of the resistance-change elements is a magnetresistive element,
the magnetresistive element includes a first magnetic layer with invariable magnetization and a second magnetic layer with variable magnetization,
the magnetresistive element has the first resistance when a direction of magnetization of the second magnetic layer is substantially opposite to a direction of magnetization of the first magnetic layer, and
the magnetresistive element has the second resistance when the direction of magnetization of the second magnetic layer is substantially same as the direction of magnetization of the first magnetic layer.
2. The memory of claim 1 , wherein the second write operation is executed after the first write operation.
3. The memory of claim 1 , wherein the first write operation is executed after the second write operation.
4. The memory of claim 1 , wherein the first and second write operations are executed in series.
5. The memory of claim 1 , wherein the first and second write operations are executed with a standby time between.
6. The memory of claim 1 , wherein the first driver applies the second potential to the control terminal of the another one of the transistors after applying the first potential to the control terminal of the another one of the transistors, and the first potential and the second potential are applied to the control terminal of the another one of the transistors in the second write operation.