Stacked die integrated circuit
An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
1. A method, comprising:
obtaining a package substrate having a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate;
etching to expose upper ends of the first plurality of via structures to provide a layer of interconnect structures extending above the upper surface of the package substrate;
obtaining a die having a second plurality of via structures extending to a lower surface of the die;
positioning the lower surface of the die for facing the upper surface of the package substrate to provide an integrated circuit package;
forming wires directly attached to lower ends of the first plurality of via structures along the lower surface of the package substrate to provide a bond via array;
depositing a molding compound along the lower surface of the package substrate over the bond via array; and
coupling the die and the package substrate to one another;
wherein the package substrate does not include a redistribution layer.
2. The method according to claim 1 , wherein the first plurality of via structures of the package substrate are respectively coupled to the second plurality of via structures of the die for a one-to-one correspondence between the first plurality of via structures and the second plurality of via structures.
3. The method according to claim 1 , wherein the first plurality of via structures are directly coupled to the second plurality of via structures.
4. The method according to claim 3 , wherein the first plurality of via structures are respectively directly coupled to the second plurality of via structures through a corresponding plurality of interconnects.
5. The method according to claim 1 , wherein the obtaining of the package substrate comprises:
obtaining a sheet of material for providing of the package substrate;
forming openings in the sheet of material for the first plurality of via structures of the package substrate; and
depositing conductive material in the openings in the sheet of material to provide conductors of the first plurality of via structures.
6. The method according to claim 5 , wherein the package substrate is formed of an inorganic material.
7. The method according to claim 5 , wherein the package substrate is formed of a material selected from a group consisting of silicon, glass, polymer, and composite.
8. A method, comprising:
obtaining a package substrate having a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate;
obtaining a die having a second plurality of via structures extending to a lower surface of the die;
coupling the die and the package substrate to one another;
wherein the lower surface of the die faces the upper surface of the package substrate in an integrated circuit package;
wherein the package substrate does not include a redistribution layer; and
etching to expose upper ends of the first plurality of via structures to provide a layer of interconnect structures extending above the upper surface of the package substrate.
9. The method according to claim 8 , further comprising plating the upper ends of the layer of interconnect structures to provide conical-shaped raised ends.
10. The method according to claim 8 , wherein the step of coupling comprises respectively coupling the first plurality of via structures of the package substrate to the second plurality of via structures of the die for a one-to-one correspondence between the first plurality of via structures and the second plurality of via structures.
11. The method according to claim 8 , wherein the first plurality of via structures have a first pitch which is equal to a second pitch of the second plurality of via structures.
12. The method according to claim 11 , wherein:
the die includes the redistribution layer disposed along an upper surface of the die;
the die is an interposer; and
the redistribution layer of the interposer is coupled to the second plurality of via structures of the interposer.
13. The method according to claim 12 , further comprising
coupling a plurality of dies to the redistribution layer of the interposer with a plurality of interconnects.
14. A method, comprising:
obtaining a package substrate having a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate;
obtaining an interposer having a second plurality of via structures extending to a lower surface of the interposer;
wherein the lower surface of the interposer faces the upper surface of the package substrate in an integrated circuit package;
wherein the package substrate does not include a redistribution layer;
coupling the interposer and the package substrate to one another;
wherein the first plurality of via structures have a first pitch which is equal to a second pitch of the second plurality of via structures;
coupling a plurality of dies to the upper surface of the interposer with a plurality of interconnects having
a third pitch having a greater density than both the first pitch and the second pitch; and
etching the package substrate to expose upper ends of the first plurality of via structures to provide a layer of micro pins extending above the upper surface of the package substrate.