Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material

1. A method of manufacturing a transistor, the method comprising:

providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material;

forming at least one layer of resist material over said regions and directly over the region of electrically conductive material, such that a bottom surface of the at least one layer of resist material is in direct contact with a top surface of the region of electrically conductive material, to form a covering of resist material over said regions;

forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of electrically conductive material, said first portion separating a second portion of the region of electrically conductive material from a third portion of the region of electrically conductive material;

removing resist material located under said depression so as to form a first window, through said covering of resist material, exposing said first portion of the region of electrically conductive material;

removing said first portion of the region of electrically conductive material to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion of the region of electrically conductive material to the third portion of the region of electrically conductive material;

forming a layer of dielectric material over the exposed connecting portion of the region of semiconductive material; and

depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the region of electrically conductive material,

whereby said second and third portions of the region of electrically conductive material provide a source terminal and a drain terminal, respectively, and

whereby the layer of electrically conductive material provides a gate terminal to which a potential may be applied to control a conductivity of the connecting portion of the region of semiconductive material connecting the second and third portions of the region of electrically conductive material.

2. The method of claim 1 , wherein said forming at least one layer of resist material comprises forming a first layer of a first resist material over said regions and directly over the region of electrically conductive material, and forming a second layer of a second resist material over the first layer.

3. The method of claim 2 , wherein said first resist material is a lift-off resist material.

4. The method of claim 2 , wherein said second resist material is an imprintable resist material.

5. The method of claim 4 , wherein forming said depression in a surface of the covering of resist material comprises forming said depression by imprinting using an imprinting tool, and wherein said surface of the covering of resist material is a surface of the second layer of resist material.

6. The method of claim 5 , wherein forming said depression in a surface of the covering of resist material is performed at the same time as forming the second layer of the second resist material.

7. The method of claim 5 , wherein forming said depression in a surface of the covering of resist material is performed after forming the second layer of the second resist material.

8. The method of claim 1 , wherein forming the layer of dielectric material over the exposed connecting portion of the region of semiconductive material comprises depositing dielectric material at least inside the first window to form the layer of dielectric material, and wherein the method further comprises:

removing resist material at least from around said first window so as to expose the second and third portions of the region of electrically conductive material.

9. The method of claim 8 , further comprising undercutting the covering of resist material around the first window before said depositing of dielectric material so as to expose a part of an upper surface of the second portion of the region of electrically conductive material adjacent the connecting portion and to expose a part of an upper surface of the third portion of the region of electrically conductive material adjacent the connecting portion of the region of semiconductive material.

10. The method of claim 9 , wherein said depositing of dielectric material is arranged such that the layer of dielectric material at least partly covers the exposed part of the upper surface of the second portion of the region of electrically conductive material and the exposed part of the upper surface of the third portion of the region of electrically conductive material.

11. The method of claim 9 , wherein said forming at least one layer of resist material over said regions to form the covering of resist material over said regions comprises forming a first layer of a first resist material over said regions and forming a second layer of a second resist material over the first layer, and wherein undercutting the covering of resist material comprises forming at least one undercut in the first layer.

12. The method of claim 9 , further comprising removing resist material to widen said first window after said undercutting but before said depositing of dielectric material.

13. The method of claim 9 , further comprising removing resist material to widen said first window at the same time as said undercutting.

14. The method of claim 1 , wherein one or more additional transistors are manufactured on the substrate to form an electronic circuit comprising an array of a plurality of transistors on the substrate, the method further comprising:

forming a covering of dielectric material over the array of transistors;

forming a plurality of windows in the covering of dielectric material, each window exposing at least a portion of a terminal of a respective transistor; and

selectively forming interconnections between said exposed portions of terminals.

15. The method of claim 14 , wherein selectively forming interconnections between said exposed portions of terminals comprises printing conductive material.

16. The method of claim 1 , further comprising:

forming a covering of dielectric material over the transistor;

forming a window in the covering of dielectric material, the window exposing the gate terminal of the transistor; and

selectively forming an interconnection between the gate terminal and another portion of conductive material supported by the substrate.