IP Library › Granted Patent US 9,806,035

Granted Patent B2

US 9,806,035 · App. 15/236,143 · Granted Oct 31, 2017

Semiconductor device

Inventors: Tadatoshi Danno (Takasaki, JP); Hiroyoshi Taya (Takasaki, JP); Yoshiharu Shimizu (Takasaki, JP)

Assignee: Renesas Electronics Corporation

H01L23/562 H01L21/4825 H01L21/4842 H01L21/565 H01L21/6715 H01L21/67144 H01L21/78 H01L23/3107 H01L23/3114 H01L23/4952 H01L23/49503 H01L23/49524 H01L23/49548 H01L23/544 H01L24/32 H01L24/83 H01L24/45 H01L24/48 H01L24/49 H01L24/73 H01L2223/54486 H01L2224/05554 H01L2224/32014 H01L2224/32245 H01L2224/45144 H01L2224/484 H01L2224/48091 H01L2224/48247 H01L2224/48599 H01L2224/49171 H01L2224/73265 H01L2924/014 H01L2924/01004 H01L2924/01005 H01L2924/01006 H01L2924/01029 H01L2924/01033 H01L2924/01046 H01L2924/01047 H01L2924/01078 H01L2924/01079 H01L2924/01082 H01L2924/12042 H01L2924/157 H01L2924/181 H01L2924/3025 H01L2924/3701

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 9,806,035
App. No.: 15/236,143
Granted: Oct 31, 2017
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Claims (66)

1. A semiconductor device, comprising:

a chip mounting portion having a first surface and a second surface opposite to the first surface;

a semiconductor chip mounted on the first surface of the chip mounting portion;

a plurality of suspension leads connected to the chip mounting portion, each of the plurality of suspension leads having a third surface located on the same side as the first surface of the chip mounting portion, and a fourth surface opposite to the third surface;

a plurality of leads arranged around the chip mounting portion in plan view, each of the plurality of leads having a fifth surface located on the same side as the first surface of the chip mounting portion, and a sixth surface opposite to the fifth surface;

a plurality of wires electrically connecting a plurality of pads of the semiconductor chip with the plurality of leads, respectively; and

a sealing body sealing the semiconductor chip and the plurality of wires, the sealing body having a top surface and a bottom surface opposite to the top surface,

wherein, in cross-section view, the first surface of the chip mounting portion is located between the top surface of the sealing body and the second surface of the chip mounting portion,

wherein, in plan view, a shape of the bottom surface is comprised of quadrangle having sides and corner portions,

wherein the plurality of suspension leads extend from the chip mounting portion toward the corner portions, respectively,

wherein the plurality of suspension leads have end portions located at the corner portions, respectively,

wherein each of the plurality of leads has a first portion and a second portion,

wherein, in cross-section view, a thickness of the second portion is less than a thickness of the first portion,

wherein the sixth surface of the second portion of each of the plurality of leads is covered with the sealing body,

wherein the sixth surface of the first portion of each of the plurality of leads is exposed from the bottom surface of the sealing body,

wherein a thickness of each of the end portions of the plurality of suspension leads is less than the thickness of the first portion of each of the plurality of leads,

wherein the fourth surface of each of the end portions of the plurality of suspension leads is covered with the sealing body,

wherein the plurality of suspension leads include a first suspension lead, a second suspension lead, a third suspension lead, and a fourth suspension lead,

wherein the plurality of leads include a first group of leads arranged along a first one of the sides and also arranged between the first suspension lead and the second suspension lead, a second group of leads arranged along a second one of the sides and also arranged between the second suspension lead and the third suspension lead, a third group of leads arranged along a third one of the sides and also arranged between the third suspension lead and the fourth suspension lead, and a fourth group of leads arranged along a fourth one of the sides and also arranged between the fourth suspension lead and the first suspension lead,

wherein the first group of leads has a first lead arranged next to the first suspension lead, a second lead arranged next to the second suspension lead, and a third lead arranged between the first lead of the first group and the second lead of the first group,

wherein the second group of leads has a first lead arranged next to the second suspension lead, a second lead arranged next to the third suspension lead, and a third lead arranged between the first lead of the second group and the second lead of the second group,

wherein the third group of leads has a first lead arranged next to the third suspension lead, a second lead arranged next to the fourth suspension lead, and a third lead arranged between the first lead of the third group and the second lead of the third group,

wherein the fourth group of leads has a first lead arranged next to the fourth suspension lead, a second lead arranged next to the first suspension lead, and a third lead arranged between the first lead of the fourth group and the second lead of the fourth group,

wherein the sixth surface of the first portion of each of the first lead of the first group and the second lead of the fourth group has a first chamfered portion along the first suspension lead, the sixth surface of the first portion of each of the first lead of the second group and the second lead of the first group has a second chamfered portion along the second suspension lead, the sixth surface of the first portion of each of the first lead of the third group and the second lead of the second group has a third chamfered portion along the third suspension lead, and the sixth surface of the first portion of each of the first lead of the fourth group and the second lead of the third group has a fourth chamfered portion along the fourth suspension lead, and

wherein the first chamfered portion of the first lead of the first group and the first chamfered portion of the second lead of the fourth group face each other,

wherein the second chamfered portion of the first lead of the second group and the second chamfered portion of the second lead of the first group face each other,

wherein the third chamfered portion of the first lead of the third group and the third chamfered portion of the second lead of the second group face each other,

wherein the fourth chamfered portion of the first lead of the fourth group and the fourth chamfered portion of the second lead of the third group face each other, and

wherein a part of the second surface of the chip mounting portion is exposed from the bottom surface of the sealing body.

2. The semiconductor device according to claim 1 , wherein the sixth surface of the first portion of each of the plurality of leads is covered with a plating layer.

3. The semiconductor device according to claim 2 , wherein the plating layer is comprised of solder or palladium.

4. The semiconductor device according to claim 1 , wherein, in plan view, the second portion extends obliquely from the first portion.

5. The semiconductor device according to claim 4 , wherein the plurality of wires are electrically connected with the plurality of leads, respectively, at the second portions of the plurality of leads.

6. A semiconductor device, comprising:

a chip mounting portion having a first surface, and a second surface opposite to the first surface;