Hybrid memory management

1. A computer-implemented method comprising:

receiving a request to access, from a main memory, a first cache line of a page of data;

determining that the first cache line is not stored in the main memory and is stored in a secondary memory, and in response,

transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory;

updating a page table entry associated with the page of data to point to a location of the page of data in the main memory; and

transferring the remaining portion of the page of data from the secondary memory to the main memory to service an access of a second cache line of the page of data, the transferring including,

issuing, by a cache agent, a request for ownership of cache lines in the page of data; and

releasing, by the cache agent, ownership by the cache agent of each cache line in response to the cache line being transferred from the secondary memory to the main memory.

2. The method of claim 1 , wherein a cache coherency mechanism is implemented while transferring the remaining portion of the page of data from the secondary memory to the main memory to service the access of the second cache line of the page of data.

3. The method of claim 1 , further comprising:

storing cache lines of the page of data in cache of the cache agent.

4. The method of claim 1 , further comprising:

storing tags and coherence state bits associated with cache lines of the page of data.

5. The method of claim 1 , further comprising:

in response to a request to access the second cache line of the page of data while the remaining portion of the page of data is being transferred, recognizing a snoop request for the second cache line, and returning the second cache line in response to the snoop request once the second cache line is transferred from the secondary memory.

6. The method of claim 1 , further comprising:

if the main memory cannot receive a page transfer, determining one of a least used pages stored in the main memory and releasing the one of the least used pages into the secondary memory, and transferring the page of data from the secondary memory to the main memory at the location of the released one of the least used pages.

7. A system comprising:

one or more processors; and

one or more storage devices storing instructions that are operable, when executed by the one or more processors, to cause the one or more processors to perform operations comprising:

receiving a request to access, from a main memory, a first cache line of a page of data;

determining that the first cache line is not stored in the main memory and is stored in a secondary memory;

transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory;

updating a page table entry associated with the page of data to point to a location of the page of data in the main memory;

transferring the remaining portion of the page of data from the secondary memory to the main memory to service an access of a second cache line of the page of data, the transferring including,

issuing, by a cache agent, a request for ownership of cache lines in the page of data; and

releasing, by the cache agent, ownership by the cache agent of each cache line in response to the cache line being transferred from the secondary memory to the main memory.

8. The system of claim 7 , wherein a cache coherency mechanism is implemented while transferring the remaining portion of the page of data from the secondary memory to the main memory to service the access of the second cache line of the page of data.

9. The system of claim 7 , the operations further comprising:

storing cache lines of the page of data in cache of the cache agent.

10. The system of claim 7 , the operations further comprising:

storing tags and coherence state bits associated with cache lines of the page of data.

11. The system of claim 7 , the operations further comprising:

in response to a request to access the second cache line of the page of data while the remaining portion of the page of data is being transferred, recognizing a snoop request for the second cache line, and returning the second cache line in response to the snoop request once the second cache line is transferred from the secondary memory.

12. The system of claim 7 , the operations further comprising:

if the main memory cannot receive a page transfer, determining one of a least used pages stored in the main memory and releasing the one of the least used pages into the secondary memory, and transferring the page of data from the secondary memory to the main memory at the location of the released one of the least used pages.

13. A computer-readable storage device storing instructions executable by one or more processors which, upon such execution, cause the one or more processors to perform operations comprising:

receiving a request to access, from a main memory, a first cache line of a page of data;

determining that the first cache line is not stored in the main memory and is stored in a secondary memory;

transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory;

updating a page table entry associated with the page of data to point to a location of the page of data in the main memory;

transferring the remaining portion of the page of data from the secondary memory to the main memory to service an access of a second cache line of the page of data, the transferring including,

issuing, by a cache agent, a request for ownership of cache lines in the page of data; and

releasing, by the cache agent, ownership by the cache agent of each cache line in response to the cache line being transferred from the secondary memory to the main memory.

14. The computer-readable storage device of claim 13 , wherein a cache coherency mechanism is implemented while transferring the remaining portion of the page of data from the secondary memory to the main memory to service the access of the second cache line of the page of data.

15. The computer-readable storage device of claim 13 , the operations further comprising:

storing one of: (i) cache lines of the page of data in cache of the cache agent or (ii) tags and coherence state bits associated with cache lines of the page of data.

16. The computer-readable storage device of claim 13 , the operations further comprising:

in response to a request to access the second cache line of the page of data while the remaining portion of the page of data is being transferred, recognizing a snoop request for the second cache line, and returning the second cache line in response to the snoop request once the second cache line is transferred from the secondary memory.

17. The computer-readable storage device of claim 13 , the operations further comprising:

if the main memory cannot receive a page transfer, determining one of a least used pages stored in the main memory and releasing the one of the least used pages into the secondary memory, and transferring the page of data from the secondary memory to the main memory at the location of the released one of the least used pages.