Method for manufacturing isolation structure

1. A method for manufacturing a semiconductor device, comprising:

forming a first trench and a second trench in a substrate, wherein the first and the second trenches are electrically connected, wherein the second trench is formed wider than the first trench;

forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench;

forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, wherein the merged overhang fills a top portion of the first trench, wherein the non-merged overhang opens a top portion of the second trench; and

forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.

2. The method according to claim 1 ,

wherein the merged overhang defines a first gap in the lower portion of the first trench,

wherein the non-merged overhang defines a second gap in the second trench,

wherein the first and the second gaps are electrically connected, and

wherein the gap-fill layer fills the first and the second gaps and extends from the second gap to the first gap.

3. The method according to claim 1 , further comprising:

planarizing the gap-fill layer and the capping layer to form an isolation structure in the first and the second trenches,

wherein the planarized gap-fill layer includes a first planarized gap-fill layer disposed in the first trench and a second planarized gap-fill layer disposed in the second trench,

wherein the first planarized gap-fill layer is completely covered by the merged overhang, and

wherein the second planarized gap-fill layer is formed over a top sidewall of the first trench.

4. The method according to claim 1 ,

wherein the capping layer is formed by plasma-enhanced chemical vapor deposition (PECVD) or low temperature atomic layer deposition (ALD).

5. The method according to claim 1 ,

wherein the capping layer includes an oxide-base material.

6. The method according to claim 1 , wherein the forming of the liner layer comprises:

forming a seed silicon layer over the inner surface of the first trench and over the inner surface of the second trench; and

forming an amorphous silicon layer over the seed silicon layer.

7. The method according to claim 6 , further comprising:

after the forming of the capping layer, converting the liner layer into a silicon oxide layer.

8. The method according to claim 7 ,

wherein the converting of the liner layer into the silicon oxide layer is performed by radical oxidation or dry oxidation.

9. The method according to claim 1 , wherein the forming of the liner layer comprises:

forming a first oxide layer over the inner surface of the first trench and over the inner surface of the second trench; and

performing an oxidation process to form a second oxide layer between the inner surfaces of the first and the second trenches and the first oxide layer.

10. The method according to claim 9 ,

wherein the oxidation process is performed by radical oxidation or dry oxidation.

11. The method according to claim 1 , wherein the forming of the gap-fill layer comprises:

forming a first dielectric layer over the capping layer, wherein the first dielectric layer substantially completely fills the first trench and partially fills the second trench; and

forming a second dielectric layer over the first dielectric layer to fill the second trench.

12. The method according to claim 11 ,

wherein the first dielectric layer includes nitride, and

wherein the second dielectric layer includes oxide.

13. The method according to claim 11 ,

wherein each of the first dielectric layer and the second dielectric layer includes nitride.

14. The method according to claim 1 , further comprising:

planarizing the gap-fill layer and the capping layer to form an isolation structure in the first and the second trenches, wherein the isolation structure defining active regions;

forming a gate trench that extends across the isolation structure and the active regions;

forming a gate dielectric layer over an inner surface of the gate trench;

forming a gate layer over the gate dielectric layer to fill the gate trench;

recessing the gate layer to form a gate electrode so that the gate electrode remains in the gate trench; and

forming a gate capping layer over the gate electrode and in the gate trench.

15. The method according to claim 14 , further comprising:

recessing the isolation structure under the gate trench to form a fin region.

16. The method according to claim 14 , wherein the forming of the gate dielectric layer comprises:

forming a silicon layer over the inner surface of the gate trench; and

converting the silicon layer into a silicon oxide layer.

17. The method according to claim 14 , wherein the forming of the gate dielectric layer comprises:

forming a silicon nitride layer over the inner surface of the gate trench; and

converting the silicon nitride layer into the silicon oxide layer.

18. The method according to claim 14 , wherein the forming of the gate dielectric layer comprises:

forming a first silicon oxide layer over the inner surface of the gate trench; and

performing an oxidation process to form a second silicon oxide layer between the inner surface of the gate trench and the first silicon oxide layer.

19. The method according to claim 14 , further comprising:

forming a first contact node and a second contact node in each of the active regions;

forming a bit line coupled to the first contact node; and

forming a memory element coupled to the second contact node.

20. The method according to claim 1 ,

wherein the first and the second trenches define active regions,

wherein the active regions comprise:

a first pair of active regions defined by the first trench and is supported by the merged overhang; and

a second pair of active regions defined by the second trench.