Granted Patent B2

US 10,078,112 · App. 15/236,182 · Granted Sep 18, 2018

Inventors: Sanjay Bhandari (San Jose, CA); Tony Maraldo (San Jose, CA)

Assignee: mCube, Inc.

G01R31/31719G01R31/3177G01R31/31701G06F21/73

Abstract

Claims (86)

1. A method for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-System) device having a MEMS sensor with an output register associated with a sensing operation, the integrated MEMS device being electrically coupled to a computing system programmed to perform the method, the method comprising:

in normal operation, reading from the output register an output of the sensing operation;

in a test mode, determining, by a processor disposed within the computing system, a random value, wherein determining the random value includes reading from the output register, which, in the test mode, provides a value from an internal pattern generator;

determining, by the processor, a validation value;

reading, by the processor, the random value stored in the output register; and

determining, by the processor, whether the integrated MEMS device is valid using the validation value and the random value stored in the output register.

2. The method of claim 1 , further comprising:

reading, by the processor, a device ID from a device ID register disposed within the integrated MEMS device; and

determining, by the processor, whether the device ID of the integrated MEMS device is valid.

3. The method of claim 1 , further comprising one or more of the following steps:

enabling, by a test module disposed within the integrated MEMS device, a test x-out process, wherein determining the random value comprises determining a random x-value and writing the random value to an out register comprises writing the random x-value to an x-out register;

enabling, by a test module disposed within the integrated MEMS device, a test g-out process, wherein determining the random value comprises determining a random y-value and writing the random value to an out register comprises writing the random y-value to a y-out register; and

enabling, by a test module disposed within the integrated MEMS device, a test t-out process, wherein determining the random value comprises determining a random z-value and writing the random value to an out register comprises writing the random z-value to an z-out register.

4. The method of claim 1 , further comprising:

determining, by the processor, a configuration value; and performing the following steps m times, where m is an integer greater than 1:

determining, by a logic module disposed within the integrated MEMS device, an operation result via a logic operation using a value stored in the output register and the configuration value, wherein the value stored in the output register on the first iteration of the steps performed m times is the random value and the value stored in the output register on each subsequent iteration of the steps performed m times is the operation result of the previous iteration of the steps performed m times; and

writing, by the processor, the operation result to the out register.

5. The method of claim 4 , wherein the random value comprises an 8-bit random value.

6. The method of claim 5 , wherein the logic operation comprises a linear transformation from 8-bit to 16-bit space through a Raw Bypass Mode (RBM) operation, the RBM operation returning an RBM value.

7. The method of claim 1 , wherein determining the random value comprises, in the test mode:

determining random x, y, and z values respectively;

writing the random x, y, and z values to X, Y, and Z output registers, respectively;

using the X, Y, and Z output registers and making combinations of the x, y, and z values.

8. The method of claim 1 , further comprising:

determining, by the processor, a validation result using a logic operation;

reading, by the processor, the operation result from the output register; and

determining, by the processor, whether the integrated MEMS device is valid using the validation result and the operation result.

9. The method of claim 1 , further comprising providing an input from the output register to the internal pattern generator related to a duty cycle of the internal pattern generator.

10. The method of claim 1 , further comprising:

determining, by the processor, a configuration value;

determining, by a logic module disposed within the integrated MEMS device, an operation result via a logic operation using the random value stored in the out register, wherein the logic operation comprises a linear feedback shift register (LSFR) operation, the LSFR operation being performed k times where k is an integer greater than or equal to 1;

reading, by the processor, the operation result, wherein reading the operation result comprises reading the operation result from a security register after waiting k clock cycles; and

writing, by the processor, the operation result to the output register.

11. A method for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-System) device having a MEMS sensor with an output register associated with a sensing operation, the integrated MEMS device being electrically coupled to a computing system programmed to perform the method, the method comprising:

in normal operation, reading from the output register an output of the sensing operation;

in a test mode, determining, by a processor disposed within the computing system, a random value, wherein determining the random value includes reading from the output register, which in the test mode provides a value from a MEMS process or provides a value from an internal pattern generator or logic module;

determining, by the processor, a validation value;

reading, by the processor, the random value stored in the output register; and

determining, by the processor, whether the integrated MEMS device is valid using the validation value and the random value stored in the output register.

12. The method of claim 11 , further comprising:

reading, by the processor, a device ID from a device ID register disposed within the integrated MEMS device; and

determining, by the processor, whether the device ID of the integrated MEMS device is valid.

13. The method of claim 11 , further comprising one or more of the following steps:

enabling, by a test module disposed within the integrated MEMS device, a test x-out process, wherein determining the random value comprises determining a random x-value and writing the random value to an out register comprises writing the random x-value to an x-out register;

enabling, by a test module disposed within the integrated MEMS device, a test g-out process, wherein determining the random value comprises determining a random y-value and writing the random value to an out register comprises writing the random y-value to a y-out register; and

enabling, by a test module disposed within the integrated MEMS device, a test t-out process, wherein determining the random value comprises determining a random z-value and writing the random value to an out register comprises writing the random z-value to an z-out register.

14. The method of claim 13 , further comprising, in the test mode,

providing an analog or digital test x-out value as output of MEMS self test electrode acting on x axis;

providing an analog or digital test y-out value as output of MEMS self test electrode acting on y axis; and

providing an analog or digital test z-out as output of MEMS self test electrode acting on z axis.

15. A method for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-Systems) device including, the integrated MEMS device configured with a MEMS sensor, a MEMS test module, and an internal pattern generator, the integrated MEMS device being further configured with an output register associated with a corresponding sensing operation, wherein, in a test mode, the output register is configured to receive a value from the internal pattern generator or internal logic, the integrated MEMS device being electrically coupled to a computing system or processor programmed to perform the method, the method comprising:

reading, by a processor disposed within the computing system, a device ID from a device ID register disposed within the integrated MEMS device;

determining, by the processor, whether the device ID of the integrated MEMS device is valid;

determining, by the processor disposed within the computing system, a random value, wherein determining the random value includes enabling, by the MEMS test module a MEMS test process to determine the random value or by setting a value associated with a duty cycle of the internal pattern generator in the output register and then reading from the output register to obtain the value from the internal pattern generator or a time stamp mechanism used by the processor;

writing, by the processor, the random value to a security register disposed within the integrated MEMS device;

determining, by the processor, a configuration value;

writing, by the processor, the configuration value to a security configuration register disposed within the integrated MEMS device;

determining, by a logic module disposed within the integrated MEMS device, an operation result via a logic operation using the random value and the configuration value;

writing, by the processor, the operation result to the security register;

independently determining, by the processor, a validation result using the same logic operation as performed by the integrated MEMS device;

reading, by the processor, the operation result from the security register; and

determining, by the processor, whether the integrated MEMS device is valid using the device ID, the validation result, and results from the independently determining performed by the processor.

16. The method of claim 15 , wherein the integrated MEMS device is configured to, based on device validation, recognize by the processor or software that the integrated MEMS device should enable or disable certain functions or features within the integrated MEMS device.

17. The method of claim 15 , wherein the integrated MEMS device is configured to provide a plurality of sensor output resolutions, including resolutions of 8-bit, 10-bit, and 14-bit.

18. The method of claim 15 , wherein the integrated MEMS device is configured with analog or digital signal processing functions activated within the MEMS sensor and subsystems within the integrated MEMS device, wherein the signal processing functions include filtering, post processing, and event detection.

19. The method of claim 15 , wherein the integrated MEMS device is configured with hardware operations enabled or disabled by the integrated MEMS device or the processor.

20. The method of claim 15 , wherein the integrated MEMS device is configured with software operations enabled or disabled by the integrated MEMS device or the processor.

21. A method for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-Systems) device including, the integrated MEMS device configured with a MEMS sensor, a MEMS test module, and an internal pattern generator, the integrated MEMS device being further configured with an output register associated with a corresponding sensing operation, wherein, in a test mode, the output register is configured to receive a value from the internal pattern generator or internal logic, the integrated MEMS device being electrically coupled to a computing system or processor programmed to perform the method, the method comprising:

reading, by a processor disposed within the computing system, a device ID from a device ID register disposed within the integrated MEMS device;

determining, by the processor, whether the device ID of the integrated MEMS device is valid;

determining, by the processor, a random value, wherein determining the random value includes enabling, by the MEMS test module, a MEMS process to determine the random value or by setting a value associated with a duty cycle of the internal pattern generator in the output register and then reading from the output register to obtain the value from the internal pattern generator or a time stamp mechanism used by the processor;

writing, by the processor, the random value to a security register disposed within the integrated MEMS device;

determining, by the processor, a configuration value;

writing, by the processor, the configuration value to a security configuration register disposed within the integrated MEMS device;

determining, by a logic module disposed within the integrated MEMS device, an operation result via a logic operation using the random value and the configuration value;

writing the operation result to the security register;

independently determining, by the processor, a validation result using the same logic operation as performed by the integrated MEMS device;

reading, by the processor, the operation result from the security register; and

determining, by the processor, whether the integrated MEMS device is valid using the device ID, the validation result, and results from the independently determining performed by the processor.

22. The method of claim 21 , wherein the MEMS process comprises a MEMS test process wherein a self test electrode electrostatically activates the MEMS sensor to produce a test value.

23. The method of claim 21 , wherein the security configuration register comprises the device ID register.

24. The method of claim 23 , wherein the logic module comprises a XOR logic module coupled to the security register and the logic operation comprises an XOR operation.

25. The method of claim 21 , wherein the logic module comprises a linear feedback shift register (LFSR) module coupled to the security register.

26. The method of claim 25 , wherein the logic operation comprises a linear feedback shift register (LSFR) operation, the LFSR operation being performed k times where k is an integer greater than or equal to 1; and

wherein reading the operation result from the security register comprises reading the operation result from the security register after waiting k clock cycles.

27. The method of claim 25 , wherein the configuration value comprises a polynomial.

Assignments (11)

Continuity (3)