Apparatuses and methods for efficient write in a cross-point array
A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
1. A method, comprising:
initializing a memory cell by applying a first voltage difference across the memory cell;
detecting a snapback event across the memory cell; and
selecting the memory cell by applying a second voltage difference across the memory cell based at least in part on detecting the snapback event, wherein the second voltage difference is different from the first voltage difference.
2. The method of claim 1 , wherein detecting the snapback event comprises:
detecting a transition of the memory cell from a first state to a second state, the second state having a lower resistance than the first state.
3. The method of claim 1 , wherein the second voltage difference has a lower magnitude than the first voltage difference.
4. The method of claim 1 , wherein the second voltage difference is applied to the memory cell within a recovery period of the memory cell after the snapback event.
5. The method of claim 1 , wherein:
applying the first voltage difference comprises applying a first voltage to a first portion of the memory cell and applying a second voltage to a second portion of the memory cell; and
applying the second voltage difference comprises applying a third voltage to the first portion of the memory cell, and applying the second voltage to the second portion of the memory cell.
6. The method of claim 1 , wherein:
applying the first voltage difference comprises applying a first voltage to a first portion of the memory cell and applying a second voltage to a second portion of the memory cell; and
applying the second voltage difference comprises applying a third voltage to the first portion of the memory cell, and applying a fourth voltage to the second portion of the memory cell.
7. The method of claim 1 , further comprising:
performing at least one of a WRITE operation or a READ operation on the memory cell based at least in part on a current associated with applying the first voltage difference.
8. The method of claim 1 , further comprising:
determining that applying the first voltage difference does not perform a WRITE operation or a READ operation; and
performing, based at least in part on the determination, a WRITE operation or a READ operation on the memory cell by applying a third voltage difference having a magnitude greater than the first voltage difference.
9. The method of claim 1 , further comprising:
deselecting the memory cell by applying a fourth voltage difference having a lower magnitude than the second voltage difference across the memory cell.
10. An apparatus, comprising:
a memory array comprising a plurality of memory cells, each of the memory cells having a first portion electrically coupled with a line of a first plurality of lines and a second portion electrically coupled with a line of a second plurality of lines; and
a driver circuit to:
initialize a memory cell from the plurality of memory cells by applying a first voltage difference across the memory cell;
detect a transition of the memory cell from a first state to a second state, wherein the second state has a lower resistance than the first state; and
select the memory cell by applying a second voltage difference across the memory cell based at least in part on detecting the transition.
11. The apparatus of claim 10 , wherein, for applying the first voltage difference, the driver circuit is configured to:
apply a first voltage to a line of the first plurality of lines that is electrically coupled with the memory cell; and
apply a second voltage to a line of the second plurality of lines that is electrically coupled with the memory cell.
12. The apparatus of claim 11 , wherein, for applying the second voltage difference, the driver circuit is configured to:
apply a third voltage to the line of the first plurality of lines that is electrically coupled with the memory cell; and
apply the second voltage to the line of the second plurality of lines that is electrically coupled with the memory cell.
13. The apparatus of claim 12 , wherein the driver circuit is configured to:
apply the third voltage to another line of the first plurality of lines while applying the first voltage difference, while applying the second voltage difference, or both.
14. The apparatus of claim 11 , wherein, for applying the second voltage difference, the driver circuit is configured to:
apply a third voltage to the line of the first plurality of lines that is electrically coupled with the memory cell; and
apply a fourth voltage to the line of the second plurality of lines that is electrically coupled with the memory cell.
15. The apparatus of claim 10 , wherein the driver circuit is configured to:
deselect the memory cell by applying a fourth voltage difference having a lower magnitude than the second voltage difference across the memory cell.
16. The apparatus of claim 15 , wherein:
applying the first voltage difference comprises applying a first voltage to a line of the first plurality of lines that is electrically coupled with the memory cell and applying a second voltage to a line of the second plurality of lines that is electrically coupled with the memory cell,
applying the second voltage difference comprises applying a third voltage to the line of the first plurality of lines that is electrically coupled with the memory cell and applying the second voltage to the line of the second plurality of lines that is electrically coupled with the memory cell; and
applying the fourth voltage difference comprises applying the third voltage to the line of the first plurality of lines that is electrically coupled with the memory cell and applying a fourth voltage to the line of the second plurality of lines that is electrically coupled with the memory cell.
17. The apparatus of claim 16 , wherein the driver circuit is configured to:
apply the third voltage to one or more other lines of the first plurality of lines while applying the first voltage difference, while applying the second voltage difference, while applying the fourth voltage difference, or a combination thereof; and
apply the fourth voltage to one or more other lines of the second plurality of lines while applying the first voltage difference, while applying the second voltage difference, while applying the fourth voltage difference, or a combination thereof.
18. An apparatus, comprising:
a memory cell; and
a driver circuit electrically coupled with the memory cell, the driver circuit configured to:
initialize the memory cell by applying a first voltage difference across the memory cell;
detect a snapback event across the memory cell; and
select the memory cell by applying a second voltage difference across the memory cell based at least in part on detecting the snapback event, wherein the second voltage difference is different from the first voltage difference.
19. The apparatus of claim 18 , wherein the second voltage difference has a lower magnitude than the first voltage difference.
20. The apparatus of claim 18 , wherein:
for applying the first voltage difference, the driver circuit is configured to:
electrically couple a first portion of the memory cell with a voltage supply having a first voltage; and
electrically couple a second portion of the memory cell with a voltage supply having a second voltage; and
for applying the second voltage difference, the driver circuit is configured to:
electrically couple the first portion of the memory cell with a voltage supply having a third voltage; and
electrically couple the second portion of the memory cell with the voltage supply having the second voltage.