Filter and capacitor using redistribution layer and micro bump layer

1. A method of forming an integrated circuit package, the method comprising:

providing a first die having a first redistribution layer (RDL);

forming at least one micro-bump line over the first RDL, wherein:

the at least one micro-bump line is disposed over and on an under bump metal (UBM) pad, the UBM pad interposed between the at least one micro-bump line and the first RDL; and

in a plan view, the at least one micro-bump line comprises a longitudinal axis and a transverse axis perpendicular to the longitudinal axis, wherein the longitudinal axis is longer than the transverse axis, and the at least one micro-bump line comprises a continuous distribution of material forming the at least one micro-bump line along an entirety of the longitudinal axis; and

forming a filter or a capacitor comprising the first RDL, the at least one micro-bump line, or both.

2. The method of claim 1 , wherein forming the at least one micro-bump line comprises forming a copper layer over the first RDL, forming a solder layer above the copper layer, and reflowing the solder layer.

3. The method of claim 1 , further comprising:

providing a second die, wherein the second die comprises a second RDL;

mounting the second die over the at least one micro-bump line, wherein the filter or the capacitor further comprises the second RDL in the second die; and

disposing an insulating material over the first die and over and around the at least one micro-bump line, wherein a portion of the insulating material is interposed between the at least one micro-bump line and the second die.

4. The method of claim 1 , wherein forming the filter comprises forming an electrically conductive layer in the first RDL.

5. The method of claim 4 , wherein forming the electrically conductive layer in the first RDL comprises disposing the electrically conductive layer in both the first RDL and the at least one micro-bump line, and at least one of the at least one micro-bump line is coupled to the first RDL.

6. The method of claim 4 , wherein forming the electrically conductive layer in the first RDL comprises coupling the first RDL and the at least one micro-bump line with at least one via.

7. The method of claim 1 , wherein providing a first die comprises providing a first die having an electrically conductive layer in a metal layer in the first die.

8. The method of claim 7 , wherein forming the filter comprises the micro-bump line and the metal layer of the first die, and the micro-bump line is coupled to the metal layer of the first die through an opening in a passivation layer of the first die.

9. The method of claim 1 , wherein forming the at least one micro-bump line comprises forming the at least one micro-bump line with a layer of copper and a layer of solder material.

10. A method of forming an integrated circuit package, the method comprising:

forming a micro-bump layer extending between a first die and a second die, wherein the micro-bump layer comprises a first micro-bump line and a second micro-bump line both between a first surface of the first die and a second surface of the second die, the first micro-bump line being electrically connected to the first die and the second die through respective connectors, the first micro-bump line providing an electrical connection between the first die and the second die, the second micro-bump line being electrically isolated from one of the first die or the second die; and

forming a filter comprising the second micro-bump line.

11. The method of claim 10 , wherein forming the filter further comprises forming an electrically conductive layer in a redistribution layer (RDL) of the first die.

12. The method of claim 11 , wherein forming the electrically conductive layer comprises disposing the electrically conductive layer in both the RDL and the micro-bump layer, and coupling at least one of the first micro-bump line or the second micro-bump line to the RDL.

13. The method of claim 11 , wherein forming the electrically conductive layer comprises coupling the RDL and the micro-bump layer with at least one via.

14. The method of claim 10 , wherein providing the first die further comprises providing an electrically conductive layer in a metal layer in the first die.

15. The method of claim 14 , wherein forming the filter comprises coupling the micro-bump layer and the metal layer of the first die and the micro-bump layer to the metal layer of the first die through an opening in a passivation layer of the first die.

16. The method of claim 10 , wherein forming the micro-bump layer comprises forming the first micro-bump line and the second micro-bump line from a layer of copper and a layer of solder material.

17. The method of claim 10 , further comprising disposing the second die over the micro-bump layer, and wherein:

providing the second die comprises providing the second die having an RDL; and

forming the filter comprises forming the filter to include the RDL.

18. A method of forming an integrated circuit package, the method comprising:

forming a first electrically conductive layer comprising a micro-bump layer disposed between a first die and a second die, the first die having a first plurality of active components formed therein, the second die having a second plurality of active components formed therein;

forming a capacitor comprising a first electrode formed in the first electrically conductive layer, the first electrode comprising a first micro-bump line formed in the micro-bump layer between a first surface of the first die and a second surface of the second die parallel to the first surface, the first micro-bump line being electrically isolated from one of the first die or the second die;

forming a second micro-bump line that is disposed between and electrically couples the first die and the second die through respective connectors; and

forming a filter comprising the first micro-bump line.

19. The method of claim 18 , forming an underfill that electrically isolates the first micro-bump line from at least one of the first die or the second die.

20. The method of claim 18 , wherein forming the capacitor further comprises forming a second electrode in the first electrically conductive layer.